xtensa: fix xtensa_wsr always writing 0
authorMax Filippov <jcmvbkbc@gmail.com>
Sun, 20 Mar 2022 16:40:14 +0000 (09:40 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 8 Apr 2022 12:39:58 +0000 (14:39 +0200)
commit1dd031eb99107bf81aa0e72399717a87da5d0433
tree5ef14fcf79f909f6ad51266d53109c2604ee517f
parentdac518bbcebf128f48b34701db8578f9f95485e3
xtensa: fix xtensa_wsr always writing 0

commit a3d0245c58f962ee99d4440ea0eaf45fb7f5a5cc upstream.

The commit cad6fade6e78 ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
replaced 'WSR' macro in the function xtensa_wsr with 'xtensa_set_sr',
but variable 'v' in the xtensa_set_sr body shadowed the argument 'v'
passed to it, resulting in wrong value written to debug registers.

Fix that by removing intermediate variable from the xtensa_set_sr
macro body.

Cc: stable@vger.kernel.org
Fixes: cad6fade6e78 ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/xtensa/include/asm/processor.h