clk: rockchip: rk3568: Add PLL rate for 292.5MHz
authorChris Morgan <macromorgan@hotmail.com>
Wed, 18 Oct 2023 15:33:55 +0000 (10:33 -0500)
committerHeiko Stuebner <heiko@sntech.de>
Thu, 16 Nov 2023 20:26:06 +0000 (21:26 +0100)
commit1af27671f62ce919f1fb76082ed81f71cb090989
treed16a0863a47c96aa8672fd497ec753b86e063858
parentb85ea95d086471afb4ad062012a4d73cd328fa86
clk: rockchip: rk3568: Add PLL rate for 292.5MHz

Add support for a PLL rate of 292.5MHz so that the Powkiddy RGB30 panel
can run at a requested 60hz (59.96, close enough).

I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231018153357.343142-2-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3568.c