drm/i915/gtt: Preallocate Braswell top-level page directory
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 23 Aug 2019 14:14:21 +0000 (15:14 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 23 Aug 2019 18:44:21 +0000 (19:44 +0100)
commit191797a892c91aec6cdffc4e05696b722d779fe3
treea0b72732aa46195ad8c42117cacc834023ba5fd2
parent6dcb85a0ad990455ae7c596e3fc966ad9c1ba9c5
drm/i915/gtt: Preallocate Braswell top-level page directory

In order for the Braswell top-level PD to remain the same from the time
of request construction to its submission onto HW, as we may be
asynchronously rewriting the page tables (thus changing the expected
register state after having already stored the old addresses in the
request), the top level PD must be preallocated.

So wave goodbye to our lazy allocation of those 4x2 pages.

v2: A little bit of write-flushing required (presumably it always has
been required, but now we are more susceptible and it is showing up!)

v3: Put back the forced-PD-reload on every batch, we can't survive
without it and explicitly marking the context for PD reload makes
Braswell turn nasty.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823141421.2398-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gem/i915_gem_context.c
drivers/gpu/drm/i915/i915_gem_gtt.c