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(parent: a719604) | patch
clk: tegra: Halve SCLK rate on Tegra20
authorDmitry Osipenko <digetx@gmail.com>
Sun, 16 May 2021 16:30:36 +0000 (19:30 +0300)
committerThierry Reding <treding@nvidia.com>
Mon, 31 May 2021 13:16:25 +0000 (15:16 +0200)
commit18a6a7150a894383e89152a820bd71d664628abd
treeeaf38bdfe17613f40f11e7932b318830641aa2ebtree | snapshot
parenta7196048cd5168096c2c4f44a3939d7a6dcd06b9commit | diff
clk: tegra: Halve SCLK rate on Tegra20

Higher SCLK rates on Tegra20 require high core voltage. The higher
clock rate may have a positive performance effect only for AHB DMA
transfers and AVP CPU, but both aren't used by upstream kernel at all.
Halve SCLK rate on Tegra20 in order to remove the high core voltage
requirement.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra20.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)