PCI: Add lane equalization register offsets
authorKrishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Fri, 28 Mar 2025 10:28:32 +0000 (15:58 +0530)
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Sat, 19 Apr 2025 14:12:43 +0000 (19:42 +0530)
commit178af54a678d08735233e070a9329651e1589587
treee17dac36e8b9f409e72f52fb7182f32ac6fe12c2
parentf9eb654fb194e7c404d4984481a18edb9b1c1d7c
PCI: Add lane equalization register offsets

As per PCIe spec 6.0.1, add PCIe lane equalization register offset for
data rates 8.0 GT/s, 32.0 GT/s and 64.0 GT/s.

Also add a macro for defining data rate 64.0 GT/s physical layer capability
ID.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250328-preset_v6-v9-4-22cfa0490518@oss.qualcomm.com
include/uapi/linux/pci_regs.h