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dt-bindings: riscv: Add SpacemiT X60 compatibles
authorYangyu Chen <cyy@cyyself.name>
Tue, 30 Jul 2024 00:28:05 +0000 (00:28 +0000)
committerYixun Lan <dlan@gentoo.org>
Thu, 16 Jan 2025 23:53:50 +0000 (07:53 +0800)
commit16c9147e6a6c6342f4b1f9909b8f914f6e4adcab
tree9ad2e536dbb3162d10bc6ef2c10ef0b320e5a94etree
parent6055c764fcd5466696e08ac69485602c6a01d9d9commit | diff
dt-bindings: riscv: Add SpacemiT X60 compatibles

The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
SoC.

Link: https://www.spacemit.com/en/spacemit-x60-core/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Documentation/devicetree/bindings/riscv/cpus.yaml diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)