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dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 13 Jul 2023 11:38:54 +0000 (19:38 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 19 Jul 2023 17:08:00 +0000 (18:08 +0100)
commit14b14a57e642e0dab9be4e9d0866fb2c4332f7c5
tree60bedcdf898484ab156b1e3fd054a6597dceebc8tree | snapshot
parent2110add84bc6e21a1bf55f2c9d1fc14d408ce2e0commit | diff
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator

Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | blame | history
include/dt-bindings/reset/starfive,jh7110-crg.h diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)