ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock
authorKeerthy <j-keerthy@ti.com>
Mon, 14 Jul 2014 10:42:16 +0000 (16:12 +0530)
committerTony Lindgren <tony@atomide.com>
Tue, 15 Jul 2014 07:16:09 +0000 (00:16 -0700)
commit147e5413696c3d385283ceda73efb2b098657477
tree84d5404e0576675dfde9b8ea0f709e25daacac4a
parent64640998a5299b03f11df2d0cd308474db09b7d9
ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock

Add divider table to optfclk_pciephy_div clock. The 8th bit of
CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1
based on if the divider value is 0x2 or 0x1.

Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the
block diagram of Clock Generator Subsystem of PCIe PHY module. The divider
value if '1' should be programmed in order to get the correct
PCIE_PHY_DIV_GCLK frequency (2.5GHz).

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/dra7xx-clocks.dtsi