dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
authorLuo Jie <quic_luoj@quicinc.com>
Tue, 10 Jun 2025 10:35:18 +0000 (18:35 +0800)
committerBjorn Andersson <andersson@kernel.org>
Wed, 18 Jun 2025 22:16:26 +0000 (17:16 -0500)
commit0c25ae62f5dc6a438b563536b5fe7fb6da3612b8
tree6e20a1ddb9ac172a75179d9285f1956424bfe96c
parent19272b37aa4f83ca52bdf9c16d5d81bdd1354494
dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC

The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.

Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h [new file with mode: 0644]