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phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out()
authorLorenzo Bianconi <lorenzo@kernel.org>
Wed, 18 Sep 2024 13:32:52 +0000 (15:32 +0200)
committerVinod Koul <vkoul@kernel.org>
Thu, 17 Oct 2024 15:22:48 +0000 (20:52 +0530)
commit09a19fb75498985cbb598f1fa43a7d2416925c30
tree36f8554503c22828927bdbe4d91067c9b8e1bedbtree
parentf2dbca169790ea1e436ffdd9ef37d7c3a4401c46commit | diff
phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out()

Fix typo configuring REG_CSR_2L_PLL_CMN_RESERVE0 register in
airoha_pcie_phy_init_clk_out routine.

Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-1-8291729a87f8@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/phy-airoha-pcie.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)