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arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes
authorSibi Sankar <quic_sibis@quicinc.com>
Wed, 30 Oct 2024 13:08:39 +0000 (18:38 +0530)
committerBjorn Andersson <andersson@kernel.org>
Fri, 16 May 2025 20:47:37 +0000 (21:47 +0100)
commit06e3c7ec804524767f529404d023993fbca9ea43
tree8d0f1902a3d58db0e3a885120a6467bcc7b253cdtree
parent9c6ee9a760c52207eae64cb6b20cd1d93c3761ffcommit | diff
arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes

Add the cpucp mailbox and sram nodes required by SCMI perf protocol
on X1E80100 SoCs.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20241030130840.2890904-2-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/x1e80100.dtsi diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)