drm/msm/dpu: enable compression bit in cfg2 for DSC
authorJun Nie <jun.nie@linaro.org>
Thu, 30 May 2024 05:56:47 +0000 (13:56 +0800)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sat, 22 Jun 2024 22:15:39 +0000 (01:15 +0300)
commit063557239c267a9256cb379b197a71a022d8c752
tree3d4475c96d068b111c0abbb90a737543d2fb6453
parent17236bc0ee0a78d58c03a28c3015b21bde5e445f
drm/msm/dpu: enable compression bit in cfg2 for DSC

Enable compression bit in cfg2 register for DSC in the DSI case
per hardware version.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/596231/
Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-3-2ab1d334c657@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h