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(parent: 4cea6b8) | patch
spi: support CS timing for HW & SW mode
authorleilk.liu <leilk.liu@mediatek.com>
Sun, 7 Feb 2021 03:09:52 +0000 (11:09 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 8 Feb 2021 11:41:22 +0000 (11:41 +0000)
commit0486d9f91d373e7f47276f30898ee0cb12656a70
tree426f4e9eea532482fddac7a59b0c1c1cf70600fftree | snapshot
parent4cea6b8cc34ee61358d681bd2009b8bac1736ffecommit | diff
spi: support CS timing for HW & SW mode

this patch supports the controller's HW CS and SW CS via use cs_gpio.

Signed-off-by: leilk.liu <leilk.liu@mediatek.com>
Link: https://lore.kernel.org/r/20210207030953.9297-3-leilk.liu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)