spi: atmel-quadspi: add support for sam9x60 qspi controller
authorTudor Ambarus <tudor.ambarus@microchip.com>
Tue, 5 Feb 2019 17:33:38 +0000 (17:33 +0000)
committerMark Brown <broonie@kernel.org>
Wed, 6 Feb 2019 17:21:00 +0000 (17:21 +0000)
commit2e5c888873586400e3e9197514995458c7f4c3e0
tree4769d95a273a94ac648d30614822b407b9bc879c
parent3a6c501e96eefb7fd83fbaf9ac29956036d02896
spi: atmel-quadspi: add support for sam9x60 qspi controller

The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory. It uses
different transfer type bits in IFR register. It has dedicated registers
to specify a read or a write instruction: Read Instruction Code Register
(RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have
identical fields.

Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test
done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/atmel-quadspi.c