regulator: anatop: Add power gating support to digital LDOs
authorPhilipp Zabel <p.zabel@pengutronix.de>
Tue, 11 Feb 2014 13:43:44 +0000 (14:43 +0100)
committerMark Brown <broonie@linaro.org>
Fri, 14 Feb 2014 20:30:47 +0000 (20:30 +0000)
commit605ebd35f059eb7dc087c4b5def1a8ce80acec55
tree32e5ada5936e28d09247d6c303ac57ddc26c1188
parent38dbfb59d1175ef458d006556061adeaa8751b72
regulator: anatop: Add power gating support to digital LDOs

The ARM, PU, and SOC LDOs in the i.MX6 PMU can completely gate
their power output. Since power gating is configured by writing
zero to the voltage target bitfield,, store a copy of the
voltage selector to be restored when reenabling the regulator.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
drivers/regulator/anatop-regulator.c