pinctrl: Add core support for Aspeed SoCs
authorAndrew Jeffery <andrew@aj.id.au>
Tue, 30 Aug 2016 07:54:24 +0000 (17:24 +0930)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 7 Sep 2016 14:48:22 +0000 (16:48 +0200)
commit4d3d0e4272d8d660f5f14f5abcf96fb4df1aa94b
treea4722451117ba7c65f2c766c67c7998faac0fdac
parent5f714700b1892f8d67495567f16c63ad7b20d6b3
pinctrl: Add core support for Aspeed SoCs

The Aspeed SoCs typically provide more than 200 pins for GPIO and other
functions. The signal enabled on a pin is determined on a priority
basis, where a given pin can provide a number of different signal types.

In addition to the priority levels, the Aspeed pin controllers describe
the signal active on a pin by compound logical expressions involving
multiple operators, registers and bits. Some difficulty arises as a
pin's function bit masks for each priority level are frequently not the
same (i.e. we cannot just flip a bit to change from a high to low
priority signal), or even in the same register(s). Some configuration
bits affect multiple pins, while in other cases the signals for a bus
must each be enabled individually.

Together, these features give rise to some complexity in the
implementation. A more complete description of the complexities is
provided in the associated header file.

The patch doesn't implement pinctrl/pinmux/pinconf for any particular
Aspeed SoC, rather it adds the framework for defining pinmux
configurations.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/Kconfig
drivers/pinctrl/Makefile
drivers/pinctrl/aspeed/Kconfig [new file with mode: 0644]
drivers/pinctrl/aspeed/Makefile [new file with mode: 0644]
drivers/pinctrl/aspeed/pinctrl-aspeed.c [new file with mode: 0644]
drivers/pinctrl/aspeed/pinctrl-aspeed.h [new file with mode: 0644]