RISC-V: Add perf platform driver based on SBI PMU extension
authorAtish Patra <atish.patra@wdc.com>
Sat, 19 Feb 2022 00:46:57 +0000 (16:46 -0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Mon, 21 Mar 2022 21:58:33 +0000 (14:58 -0700)
commite9991434596f5373dfd75857b445eb92a9253c56
treeb39e3c364207841faf568f86332c8a087b8fe622
parent90beae5185c260074db409241247630036cf93a0
RISC-V: Add perf platform driver based on SBI PMU extension

RISC-V SBI specification added a PMU extension that allows to configure
start/stop any pmu counter. The RISC-V perf can use most of the generic
perf features except interrupt overflow and event filtering based on
privilege mode which will be added in future.

It also allows to monitor a handful of firmware counters that can provide
insights into firmware activity during a performance analysis.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
drivers/perf/Kconfig
drivers/perf/Makefile
drivers/perf/riscv_pmu.c
drivers/perf/riscv_pmu_sbi.c [new file with mode: 0644]
include/linux/cpuhotplug.h
include/linux/perf/riscv_pmu.h