perf: ARM DynamIQ Shared Unit PMU support
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Tue, 2 Jan 2018 11:25:33 +0000 (11:25 +0000)
committerWill Deacon <will.deacon@arm.com>
Tue, 2 Jan 2018 16:43:12 +0000 (16:43 +0000)
commit7520fa99246dade7ab6dde1573a146beed632abd
tree06a4763f3370fb4fb2365924540330a4ee156bcc
parent9249dee611d6624bc9044fdf3877ace67d6143ab
perf: ARM DynamIQ Shared Unit PMU support

Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events related to L3, SCU etc, along with
providing a cycle counter.

The PMU can be accessed via system registers, which are common
to the cores in the same cluster. The PMU registers follow the
semantics of the ARMv8 PMU, mostly, with the exception that
the counters record the cluster wide events.

This driver is mostly based on the ARMv8 and CCI PMU drivers.
The driver only supports ARM64 at the moment. It can be extended
to support ARM32 by providing register accessors like we do in
arch/arm64/include/arm_dsu_pmu.h.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Documentation/perf/arm_dsu_pmu.txt [new file with mode: 0644]
arch/arm64/include/asm/arm_dsu_pmu.h [new file with mode: 0644]
drivers/perf/Kconfig
drivers/perf/Makefile
drivers/perf/arm_dsu_pmu.c [new file with mode: 0644]