i40e: Handle PE_CRITERR properly with IWARP enabled
authorCatherine Sullivan <catherine.sullivan@intel.com>
Wed, 7 Jun 2017 09:43:12 +0000 (05:43 -0400)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Wed, 21 Jun 2017 01:17:12 +0000 (18:17 -0700)
commit7642984b08760b8d0ff7f4cfbe524bb53eb4cec2
treed0fb5cf7f3f8238d5c262332e72a37fb372b2b1c
parent2e5c26ea0d0843074a1b8c868aae5c828c155569
i40e: Handle PE_CRITERR properly with IWARP enabled

When IWARP is enabled, we weren't clearing the PE_CRITERR, just logging
it and removing it from the mask. We need to do a corer to reset the
PE_CRITERR register, so set the bit for that as we handle the
interrupt.

We should also be checking for the error against the PFINT_ICR0 register,
and only need to clear it in the value getting written to
PFINT_ICR0_ENA.

Signed-off-by: Catherine Sullivan <catherine.sullivan@intel.com>
Signed-off-by: Mitch Williams <mitch.a.williams@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/i40e/i40e_main.c