drm/i915: Make sure DC writes are coherent on flush.
authorFrancisco Jerez <currojerez@riseup.net>
Thu, 14 Jan 2016 02:59:39 +0000 (18:59 -0800)
committerJani Nikula <jani.nikula@intel.com>
Fri, 15 Jan 2016 09:33:52 +0000 (11:33 +0200)
commit965fd602a6436f689f4f2fe40a6789582778ccd5
tree118879b2d2ac12db5e8d499f582127fed575e8f4
parentd890565c44447db08fd9d07f5b02928a07a88c7e
drm/i915: Make sure DC writes are coherent on flush.

We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
that writes performed via the HDC are visible in memory.  Fixes an
intermittent failure in a Piglit test that writes to a BO from a
shader using GL atomic counters (implemented as HDC untyped atomics)
and then expects the memory to read back the same value after mapping
it on the CPU.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
Tested-by: Mark Janes <mark.a.janes@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1452740379-3194-1-git-send-email-currojerez@riseup.net
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_lrc.c
drivers/gpu/drm/i915/intel_ringbuffer.c