drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
authorManasi Navare <manasi.d.navare@intel.com>
Fri, 13 Jul 2018 19:43:13 +0000 (12:43 -0700)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Tue, 24 Jul 2018 22:14:53 +0000 (15:14 -0700)
commita38bb309c2ce25a562819949a19fefa38ae8ab96
tree9ee36f4df2bfa511590f712220121e3db74bdc06
parenta5b22b5ed88bfb848d40d3c593f5506bdb75c882
drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI

This patch adds the remaining register definitions and bit fields
required for MG PHy DDI buffer initializations and voltage
swing programming for MG PHy DDI ports.

While at it this patch also fixes the naming for previously defined
MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
Add register defs for voltage swing sequences for MG PHY DDI").
Since the MG PHY registers are first defined in ICL platform, there
is no need for _ICL prefix.

v4 (from Paulo): add two white spaces to CRI_CALCINIT too.

v3:
* Fix register names, add spaces for MASK defines, correct the order
of #defines (Paulo)

v2:
* Change the MG_TX_DRVCTL registers names to match the spec (Anusha)

Cc: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1531510993-6606-1-git-send-email-manasi.d.navare@intel.com
drivers/gpu/drm/i915/i915_reg.h