drm/i915: CP_IRQ handling for DP HDCP2.2 msgs
authorRamalingam C <ramalingam.c@intel.com>
Sat, 16 Feb 2019 17:37:02 +0000 (23:07 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 20 Feb 2019 19:41:59 +0000 (20:41 +0100)
commitcf9cb35ff731a784bdbb9ce621faa34346066a39
tree079d203b5140e56845b1d9d00699e9dae5ef5a61
parent2d4254e50649d2bd13f73e1513708f746a513bc1
drm/i915: CP_IRQ handling for DP HDCP2.2 msgs

Implements the
Waitqueue is created to wait for CP_IRQ
Signaling the CP_IRQ arrival through atomic variable.
For applicable DP HDCP2.2 msgs read wait for CP_IRQ.

As per HDCP2.2 spec "HDCP Transmitters must process CP_IRQ interrupts
when they are received from HDCP Receivers"

Without CP_IRQ processing, DP HDCP2.2 H_Prime msg was getting corrupted
while reading it based on corresponding status bit. This creates the
random failures in reading the DP HDCP2.2 msgs.

v2:
  CP_IRQ arrival is tracked based on the atomic val inc [daniel]
  Recording the reviewed-by Daniel from IRC.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/1550338640-17470-16-git-send-email-ramalingam.c@intel.com
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_hdcp.c