ARC: clk: introduce HSDK pll driver
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Fri, 25 Aug 2017 17:39:14 +0000 (20:39 +0300)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 31 Aug 2017 05:36:05 +0000 (22:36 -0700)
commitdaeeb438c052e3763617c636943e07a8f3684e9e
tree5db2bde1740022066098ae70919e7a14093a4e22
parent59273246b2df45feaea05e1069914f8ec2120c8c
ARC: clk: introduce HSDK pll driver

HSDK board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the
HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt [new file with mode: 0644]
MAINTAINERS
drivers/clk/Kconfig
drivers/clk/Makefile
drivers/clk/clk-hsdk-pll.c [new file with mode: 0644]