KVM: x86: optimize delivery of TSC deadline timer interrupt
authorPaolo Bonzini <pbonzini@redhat.com>
Fri, 6 Feb 2015 11:58:42 +0000 (12:58 +0100)
committerPaolo Bonzini <pbonzini@redhat.com>
Wed, 8 Apr 2015 08:46:54 +0000 (10:46 +0200)
commit9c8fd1ba2201c072bd3cf6940e2ca4d0a7aed723
treecd49f3c0f47344a99e6337da700527ff10ff7a21
parent362c698f8220e636edf1c40b1935715fa57f492f
KVM: x86: optimize delivery of TSC deadline timer interrupt

The newly-added tracepoint shows the following results on
the tscdeadline_latency test:

        qemu-kvm-8387  [002]  6425.558974: kvm_vcpu_wakeup:      poll time 10407 ns
        qemu-kvm-8387  [002]  6425.558984: kvm_vcpu_wakeup:      poll time 0 ns
        qemu-kvm-8387  [002]  6425.561242: kvm_vcpu_wakeup:      poll time 10477 ns
        qemu-kvm-8387  [002]  6425.561251: kvm_vcpu_wakeup:      poll time 0 ns

and so on.  This is because we need to go through kvm_vcpu_block again
after the timer IRQ is injected.  Avoid it by polling once before
entering kvm_vcpu_block.

On my machine (Xeon E5 Sandy Bridge) this removes about 500 cycles (7%)
from the latency of the TSC deadline timer.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/kvm/x86.c