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(parent: 86f5201) | patch
KVM: x86: Add Intel PT context switch for each vcpu
authorChao Peng <chao.p.peng@linux.intel.com>
Wed, 24 Oct 2018 08:05:12 +0000 (16:05 +0800)
committerPaolo Bonzini <pbonzini@redhat.com>
Fri, 21 Dec 2018 10:28:35 +0000 (11:28 +0100)
commit2ef444f1600bfc2d8522df0f537aafef79befa7e
tree1bdc097495a69ed493a21ef07cb07e77db0da902tree | snapshot
parent86f5201df0d3e3efc78d3eac7fc5a59b813287cdcommit | diff
KVM: x86: Add Intel PT context switch for each vcpu

Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/kvm/vmx/vmx.c diff | blob | blame | history
arch/x86/kvm/vmx/vmx.h diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)