x86/events: Add Hygon Dhyana support to PMU infrastructure
authorPu Wen <puwen@hygon.cn>
Sun, 23 Sep 2018 09:34:47 +0000 (17:34 +0800)
committerBorislav Petkov <bp@suse.de>
Thu, 27 Sep 2018 16:28:57 +0000 (18:28 +0200)
commit6d0ef316b9f8ea03fa867debda70b2f11a0b9736
treefedc78b52d0dd05ba9183c9c83ece2216d408aec
parent0b13bec787dccca96f8c431da732657ae01baf9a
x86/events: Add Hygon Dhyana support to PMU infrastructure

The PMU architecture for the Hygon Dhyana CPU is similar to the AMD
Family 17h one. To support it, call amd_pmu_init() to share the AMD PMU
initialization flow, and change the PMU name to "HYGON".

The Hygon Dhyana CPU supports both legacy and extension PMC MSRs (perf
counter registers and event selection registers), so add Hygon Dhyana
support in the similar way as AMD does.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Link: https://lkml.kernel.org/r/9d93ed54a975f33ef7247e0967960f4ce5d3d990.1537533369.git.puwen@hygon.cn
arch/x86/events/amd/core.c
arch/x86/events/amd/uncore.c
arch/x86/events/core.c
arch/x86/kernel/cpu/perfctr-watchdog.c