KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata
authorJames Morse <james.morse@arm.com>
Thu, 27 Jan 2022 12:20:52 +0000 (12:20 +0000)
committerMarc Zyngier <maz@kernel.org>
Thu, 3 Feb 2022 09:22:30 +0000 (09:22 +0000)
commit1dd498e5e26ad71e3e9130daf72cfb6a693fee03
tree9c2342019c364c0a3035ccc2297f065a51de8b23
parent1229630af88620f6e3a621a1ebd1ca14d9340df7
KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata

Cortex-A510's erratum #2077057 causes SPSR_EL2 to be corrupted when
single-stepping authenticated ERET instructions. A single step is
expected, but a pointer authentication trap is taken instead. The
erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
EL1 to cause a return to EL2 with a guest controlled ELR_EL2.

Because the conditions require an ERET into active-not-pending state,
this is only a problem for the EL2 when EL2 is stepping EL1. In this case
the previous SPSR_EL2 value is preserved in struct kvm_vcpu, and can be
restored.

Cc: stable@vger.kernel.org # 53960faf2b73: arm64: Add Cortex-A510 CPU part definition
Cc: stable@vger.kernel.org
Signed-off-by: James Morse <james.morse@arm.com>
[maz: fixup cpucaps ordering]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220127122052.1584324-5-james.morse@arm.com
Documentation/arm64/silicon-errata.rst
arch/arm64/Kconfig
arch/arm64/kernel/cpu_errata.c
arch/arm64/kvm/hyp/include/hyp/switch.h
arch/arm64/tools/cpucaps