ARM: mvebu: use DT properties to fine-tune the L2 configuration
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thu, 11 Jun 2015 11:51:12 +0000 (13:51 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Thu, 9 Jul 2015 12:25:28 +0000 (14:25 +0200)
commitc8f5a878e55459b78bac273f6492bbc91475beb5
tree922d9159d6dcf7fdee7dfe37651f7a30ced01688
parent449e1d649c52a80db73dd313dce92d6e191b801b
ARM: mvebu: use DT properties to fine-tune the L2 configuration

In order to optimize the L2 cache performance, this commit adjusts the
configuration of the L2 on the Cortex-A9 based Marvell EBU processors
(Armada 375, 38x and 39x), using the appropriate DT properties.

We enable double linefill, incr double linefill, data prefetch and
disable double linefill on wrap. This matches the configuration that
was fine tuned in the Marvell BSP.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm/boot/dts/armada-375.dtsi
arch/arm/boot/dts/armada-38x.dtsi
arch/arm/boot/dts/armada-39x.dtsi