i, val, twl4030_reg[i]);
}
}
- dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
+ dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
difference, difference ? "Not OK" : "OK");
}
u8 mode;
/* If the system master clock is not 26MHz, the voice PCM interface is
- * not avilable.
+ * not available.
*/
if (twl4030->sysclk != 26000) {
dev_err(codec->dev, "The board is configured for %u Hz, while"
}
/* If the codec mode is not option2, the voice PCM interface is not
- * avilable.
+ * available.
*/
mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
& TWL4030_OPT_MODE;