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Merge tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[linux-block.git] / sound / soc / codecs / cs35l45-tables.c
diff --git a/sound/soc/codecs/cs35l45-tables.c b/sound/soc/codecs/cs35l45-tables.c
index 4b1320a2e6e97fda9bbab2f72726b1f838543853..46610e64e8188506991c152bb078e32bc3c8b709 100644 (file)
--- a/sound/soc/codecs/cs35l45-tables.c
+++ b/sound/soc/codecs/cs35l45-tables.c
@@ -43,6 +43,12 @@ EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45);
 static const struct reg_default cs35l45_defaults[] = {
        { CS35L45_BLOCK_ENABLES,                0x00003323 },
        { CS35L45_BLOCK_ENABLES2,               0x00000010 },
+       { CS35L45_SYNC_GPIO1,                   0x00000007 },
+       { CS35L45_INTB_GPIO2_MCLK_REF,          0x00000005 },
+       { CS35L45_GPIO3,                        0x00000005 },
+       { CS35L45_PWRMGT_CTL,                   0x00000000 },
+       { CS35L45_WAKESRC_CTL,                  0x00000008 },
+       { CS35L45_WKI2C_CTL,                    0x00000030 },
        { CS35L45_REFCLK_INPUT,                 0x00000510 },
        { CS35L45_GLOBAL_SAMPLE_RATE,           0x00000003 },
        { CS35L45_ASP_ENABLES1,                 0x00000000 },
@@ -60,7 +66,53 @@ static const struct reg_default cs35l45_defaults[] = {
        { CS35L45_ASPTX3_INPUT,                 0x00000020 },
        { CS35L45_ASPTX4_INPUT,                 0x00000028 },
        { CS35L45_ASPTX5_INPUT,                 0x00000048 },
+       { CS35L45_DSP1_RX1_RATE,                0x00000001 },
+       { CS35L45_DSP1_RX2_RATE,                0x00000001 },
+       { CS35L45_DSP1_RX3_RATE,                0x00000001 },
+       { CS35L45_DSP1_RX4_RATE,                0x00000001 },
+       { CS35L45_DSP1_RX5_RATE,                0x00000001 },
+       { CS35L45_DSP1_RX6_RATE,                0x00000001 },
+       { CS35L45_DSP1_RX7_RATE,                0x00000001 },
+       { CS35L45_DSP1_RX8_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX1_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX2_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX3_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX4_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX5_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX6_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX7_RATE,                0x00000001 },
+       { CS35L45_DSP1_TX8_RATE,                0x00000001 },
+       { CS35L45_DSP1RX1_INPUT,                0x00000008 },
+       { CS35L45_DSP1RX2_INPUT,                0x00000009 },
+       { CS35L45_DSP1RX3_INPUT,                0x00000018 },
+       { CS35L45_DSP1RX4_INPUT,                0x00000019 },
+       { CS35L45_DSP1RX5_INPUT,                0x00000020 },
+       { CS35L45_DSP1RX6_INPUT,                0x00000028 },
+       { CS35L45_DSP1RX7_INPUT,                0x0000003A },
+       { CS35L45_DSP1RX8_INPUT,                0x00000028 },
        { CS35L45_AMP_PCM_CONTROL,              0x00100000 },
+       { CS35L45_IRQ1_CFG,                     0x00000000 },
+       { CS35L45_IRQ1_MASK_1,                  0xBFEFFFBF },
+       { CS35L45_IRQ1_MASK_2,                  0xFFFFFFFF },
+       { CS35L45_IRQ1_MASK_3,                  0xFFFF87FF },
+       { CS35L45_IRQ1_MASK_4,                  0xF8FFFFFF },
+       { CS35L45_IRQ1_MASK_5,                  0x0EF80000 },
+       { CS35L45_IRQ1_MASK_6,                  0x00000000 },
+       { CS35L45_IRQ1_MASK_7,                  0xFFFFFF78 },
+       { CS35L45_IRQ1_MASK_8,                  0x00003FFF },
+       { CS35L45_IRQ1_MASK_9,                  0x00000000 },
+       { CS35L45_IRQ1_MASK_10,                 0x00000000 },
+       { CS35L45_IRQ1_MASK_11,                 0x00000000 },
+       { CS35L45_IRQ1_MASK_12,                 0x00000000 },
+       { CS35L45_IRQ1_MASK_13,                 0x00000000 },
+       { CS35L45_IRQ1_MASK_14,                 0x00000001 },
+       { CS35L45_IRQ1_MASK_15,                 0x00000000 },
+       { CS35L45_IRQ1_MASK_16,                 0x00000000 },
+       { CS35L45_IRQ1_MASK_17,                 0x00000000 },
+       { CS35L45_IRQ1_MASK_18,                 0x3FE5D0FF },
+       { CS35L45_GPIO1_CTRL1,                  0x81000001 },
+       { CS35L45_GPIO2_CTRL1,                  0x81000001 },
+       { CS35L45_GPIO3_CTRL1,                  0x81000001 },
 };
 
 static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
@@ -72,6 +124,13 @@ static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
        case CS35L45_BLOCK_ENABLES:
        case CS35L45_BLOCK_ENABLES2:
        case CS35L45_ERROR_RELEASE:
+       case CS35L45_SYNC_GPIO1:
+       case CS35L45_INTB_GPIO2_MCLK_REF:
+       case CS35L45_GPIO3:
+       case CS35L45_PWRMGT_CTL:
+       case CS35L45_WAKESRC_CTL:
+       case CS35L45_WKI2C_CTL:
+       case CS35L45_PWRMGT_STS:
        case CS35L45_REFCLK_INPUT:
        case CS35L45_GLOBAL_SAMPLE_RATE:
        case CS35L45_ASP_ENABLES1:
@@ -89,9 +148,59 @@ static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
        case CS35L45_ASPTX3_INPUT:
        case CS35L45_ASPTX4_INPUT:
        case CS35L45_ASPTX5_INPUT:
+       case CS35L45_DSP1RX1_INPUT:
+       case CS35L45_DSP1RX2_INPUT:
+       case CS35L45_DSP1RX3_INPUT:
+       case CS35L45_DSP1RX4_INPUT:
+       case CS35L45_DSP1RX5_INPUT:
+       case CS35L45_DSP1RX6_INPUT:
+       case CS35L45_DSP1RX7_INPUT:
+       case CS35L45_DSP1RX8_INPUT:
        case CS35L45_AMP_PCM_CONTROL:
        case CS35L45_AMP_PCM_HPF_TST:
-       case CS35L45_IRQ1_EINT_4:
+       case CS35L45_IRQ1_CFG:
+       case CS35L45_IRQ1_STATUS:
+       case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
+       case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
+       case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
+       case CS35L45_GPIO_STATUS1:
+       case CS35L45_GPIO1_CTRL1:
+       case CS35L45_GPIO2_CTRL1:
+       case CS35L45_GPIO3_CTRL1:
+       case CS35L45_DSP_MBOX_1:
+       case CS35L45_DSP_MBOX_2:
+       case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
+       case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
+       case CS35L45_DSP1_SYS_ID:
+       case CS35L45_DSP1_CLOCK_FREQ:
+       case CS35L45_DSP1_RX1_RATE:
+       case CS35L45_DSP1_RX2_RATE:
+       case CS35L45_DSP1_RX3_RATE:
+       case CS35L45_DSP1_RX4_RATE:
+       case CS35L45_DSP1_RX5_RATE:
+       case CS35L45_DSP1_RX6_RATE:
+       case CS35L45_DSP1_RX7_RATE:
+       case CS35L45_DSP1_RX8_RATE:
+       case CS35L45_DSP1_TX1_RATE:
+       case CS35L45_DSP1_TX2_RATE:
+       case CS35L45_DSP1_TX3_RATE:
+       case CS35L45_DSP1_TX4_RATE:
+       case CS35L45_DSP1_TX5_RATE:
+       case CS35L45_DSP1_TX6_RATE:
+       case CS35L45_DSP1_TX7_RATE:
+       case CS35L45_DSP1_TX8_RATE:
+       case CS35L45_DSP1_SCRATCH1:
+       case CS35L45_DSP1_SCRATCH2:
+       case CS35L45_DSP1_SCRATCH3:
+       case CS35L45_DSP1_SCRATCH4:
+       case CS35L45_DSP1_CCM_CORE_CONTROL:
+       case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
+       case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
+       case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
+       case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
+       case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
+       case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
+       case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
                return true;
        default:
                return false;
@@ -106,7 +215,29 @@ static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
        case CS35L45_GLOBAL_ENABLES:
        case CS35L45_ERROR_RELEASE:
        case CS35L45_AMP_PCM_HPF_TST:   /* not cachable */
-       case CS35L45_IRQ1_EINT_4:
+       case CS35L45_PWRMGT_STS:
+       case CS35L45_IRQ1_STATUS:
+       case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
+       case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
+       case CS35L45_GPIO_STATUS1:
+       case CS35L45_DSP_MBOX_1:
+       case CS35L45_DSP_MBOX_2:
+       case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
+       case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
+       case CS35L45_DSP1_SYS_ID:
+       case CS35L45_DSP1_CLOCK_FREQ:
+       case CS35L45_DSP1_SCRATCH1:
+       case CS35L45_DSP1_SCRATCH2:
+       case CS35L45_DSP1_SCRATCH3:
+       case CS35L45_DSP1_SCRATCH4:
+       case CS35L45_DSP1_CCM_CORE_CONTROL:
+       case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
+       case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
+       case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
+       case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
+       case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
+       case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
+       case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
                return true;
        default:
                return false;
Linux 6.x block layer and io_uring tree(s)