Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

[linux-2.6-block.git] / sound / pci / hda / hda_intel.c

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 637b8a0e2a91d3ab9b73ddc8a4b9fc4a24303e00..9a0d1445ca5cf85c774a6f4e4be1d5a44770adad 100644 (file)
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -857,50 +857,6 @@ static int param_set_xint(const char *val, const struct kernel_param *kp)
 #define azx_del_card_list(chip) /* NOP */
 #endif /* CONFIG_PM */
 
-/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
- * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
- * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
- * BCLK = CDCLK * M / N
- * The values will be lost when the display power well is disabled and need to
- * be restored to avoid abnormal playback speed.
- */
-static void haswell_set_bclk(struct hda_intel *hda)
-{
-       struct azx *chip = &hda->chip;
-       int cdclk_freq;
-       unsigned int bclk_m, bclk_n;
-
-       if (!hda->need_i915_power)
-               return;
-
-       cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
-       switch (cdclk_freq) {
-       case 337500:
-               bclk_m = 16;
-               bclk_n = 225;
-               break;
-
-       case 450000:
-       default: /* default CDCLK 450MHz */
-               bclk_m = 4;
-               bclk_n = 75;
-               break;
-
-       case 540000:
-               bclk_m = 4;
-               bclk_n = 90;
-               break;
-
-       case 675000:
-               bclk_m = 8;
-               bclk_n = 225;
-               break;
-       }
-
-       azx_writew(chip, HSW_EM4, bclk_m);
-       azx_writew(chip, HSW_EM5, bclk_n);
-}
-
 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 /*
  * power management
@@ -958,7 +914,7 @@ static int azx_resume(struct device *dev)
        if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
                && hda->need_i915_power) {
                snd_hdac_display_power(azx_bus(chip), true);
-               haswell_set_bclk(hda);
+               snd_hdac_i915_set_bclk(azx_bus(chip));
        }
        if (chip->msi)
                if (pci_enable_msi(pci) < 0)
@@ -1058,7 +1014,7 @@ static int azx_runtime_resume(struct device *dev)
                bus = azx_bus(chip);
                if (hda->need_i915_power) {
                        snd_hdac_display_power(bus, true);
-                       haswell_set_bclk(hda);
+                       snd_hdac_i915_set_bclk(bus);
                } else {
                        /* toggle codec wakeup bit for STATESTS read */
                        snd_hdac_set_codec_wakeup(bus, true);
@@ -1796,12 +1752,8 @@ static int azx_first_init(struct azx *chip)
        /* initialize chip */
        azx_init_pci(chip);
 
-       if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
-               struct hda_intel *hda;
-
-               hda = container_of(chip, struct hda_intel, chip);
-               haswell_set_bclk(hda);
-       }
+       if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
+               snd_hdac_i915_set_bclk(bus);
 
        hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);