drm/amdgpu:new ids flag for preempt

[linux-2.6-block.git] / include / uapi / drm / amdgpu_drm.h

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index cdecf87576e890f48c7e93830c920fa33ff9b85e..4684f378f046e2cda38d655d50e3899130987a03 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -77,6 +77,12 @@ extern "C" {
 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS                (1 << 1)
 /* Flag that USWC attributes should be used for GTT */
 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC         (1 << 2)
+/* Flag that the memory should be in VRAM and cleared */
+#define AMDGPU_GEM_CREATE_VRAM_CLEARED         (1 << 3)
+/* Flag that create shadow bo(GTT) while allocating vram bo */
+#define AMDGPU_GEM_CREATE_SHADOW               (1 << 4)
+/* Flag that allocating the BO should use linear VRAM */
+#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS      (1 << 5)
 
 struct drm_amdgpu_gem_create_in  {
        /** the requested memory size */
@@ -432,6 +438,7 @@ struct drm_amdgpu_cs_chunk_data {
  *
  */
 #define AMDGPU_IDS_FLAGS_FUSION         0x1
+#define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 
 /* indicate if acceleration can be working */
 #define AMDGPU_INFO_ACCEL_WORKING              0x00
@@ -481,12 +488,34 @@ struct drm_amdgpu_cs_chunk_data {
 #define AMDGPU_INFO_DEV_INFO                   0x16
 /* visible vram usage */
 #define AMDGPU_INFO_VIS_VRAM_USAGE             0x17
+/* number of TTM buffer evictions */
+#define AMDGPU_INFO_NUM_EVICTIONS              0x18
+/* Query memory about VRAM and GTT domains */
+#define AMDGPU_INFO_MEMORY                     0x19
+/* Query vce clock table */
+#define AMDGPU_INFO_VCE_CLOCK_TABLE            0x1A
 
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK  0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
 #define AMDGPU_INFO_MMR_SH_INDEX_MASK  0xff
 
+struct drm_amdgpu_query_fw {
+       /** AMDGPU_INFO_FW_* */
+       __u32 fw_type;
+       /**
+        * Index of the IP if there are more IPs of
+        * the same type.
+        */
+       __u32 ip_instance;
+       /**
+        * Index of the engine. Whether this is used depends
+        * on the firmware type. (e.g. MEC, SDMA)
+        */
+       __u32 index;
+       __u32 _pad;
+};
+
 /* Input structure for the INFO ioctl */
 struct drm_amdgpu_info {
        /* Where the return value will be stored */
@@ -522,21 +551,7 @@ struct drm_amdgpu_info {
                        __u32 flags;
                } read_mmr_reg;
 
-               struct {
-                       /** AMDGPU_INFO_FW_* */
-                       __u32 fw_type;
-                       /**
-                        * Index of the IP if there are more IPs of
-                        * the same type.
-                        */
-                       __u32 ip_instance;
-                       /**
-                        * Index of the engine. Whether this is used depends
-                        * on the firmware type. (e.g. MEC, SDMA)
-                        */
-                       __u32 index;
-                       __u32 _pad;
-               } query_fw;
+               struct drm_amdgpu_query_fw query_fw;
        };
 };
 
@@ -564,6 +579,34 @@ struct drm_amdgpu_info_vram_gtt {
        __u64 gtt_size;
 };
 
+struct drm_amdgpu_heap_info {
+       /** max. physical memory */
+       __u64 total_heap_size;
+
+       /** Theoretical max. available memory in the given heap */
+       __u64 usable_heap_size;
+
+       /**
+        * Number of bytes allocated in the heap. This includes all processes
+        * and private allocations in the kernel. It changes when new buffers
+        * are allocated, freed, and moved. It cannot be larger than
+        * heap_size.
+        */
+       __u64 heap_usage;
+
+       /**
+        * Theoretical possible max. size of buffer which
+        * could be allocated in the given heap
+        */
+       __u64 max_allocation;
+};
+
+struct drm_amdgpu_memory_info {
+       struct drm_amdgpu_heap_info vram;
+       struct drm_amdgpu_heap_info cpu_accessible_vram;
+       struct drm_amdgpu_heap_info gtt;
+};
+
 struct drm_amdgpu_info_firmware {
        __u32 ver;
        __u32 feature;
@@ -637,10 +680,29 @@ struct drm_amdgpu_info_hw_ip {
        __u32  _pad;
 };
 
+#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES         6
+
+struct drm_amdgpu_info_vce_clock_table_entry {
+       /** System clock */
+       __u32 sclk;
+       /** Memory clock */
+       __u32 mclk;
+       /** VCE clock */
+       __u32 eclk;
+       __u32 pad;
+};
+
+struct drm_amdgpu_info_vce_clock_table {
+       struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
+       __u32 num_valid_entries;
+       __u32 pad;
+};
+
 /*
  * Supported GPU families
  */
 #define AMDGPU_FAMILY_UNKNOWN                  0
+#define AMDGPU_FAMILY_SI                       110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
 #define AMDGPU_FAMILY_CI                       120 /* Bonaire, Hawaii */
 #define AMDGPU_FAMILY_KV                       125 /* Kaveri, Kabini, Mullins */
 #define AMDGPU_FAMILY_VI                       130 /* Iceland, Tonga */