PCI: Cache MSI/MSI-X capability offsets in struct pci_dev

[linux-2.6-block.git] / include / linux / pci.h

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2461033a798728203f456eff4d6a0099816a7072..b73c2460ad57d1b267bf654df20fe1da68bd37d4 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -232,6 +232,8 @@ struct pci_dev {
        u8              revision;       /* PCI revision, low byte of class word */
        u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
        u8              pcie_cap;       /* PCI-E capability offset */
+       u8              msi_cap;        /* MSI capability offset */
+       u8              msix_cap;       /* MSI-X capability offset */
        u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
        u8              rom_base_reg;   /* which config register controls the ROM */
        u8              pin;            /* which interrupt pin this device uses */
@@ -249,8 +251,7 @@ struct pci_dev {
        pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
                                           this is D0-D3, D0 being fully functional,
                                           and D3 being off. */
-       int             pm_cap;         /* PM capability offset in the
-                                          configuration space */
+       u8              pm_cap;         /* PM capability offset */
        unsigned int    pme_support:5;  /* Bitmask of states from which PME#
                                           can be generated */
        unsigned int    pme_interrupt:1;