net/mlx5: Introduce blue flame register allocator

[linux-2.6-block.git] / include / linux / mlx5 / mlx5_ifc.h

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 57bec544e20a81070d999fc59253d0774a4c6c3b..1223feff0ea4fc372f50687a20f730d9a8b51cb6 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -328,7 +328,7 @@ struct mlx5_ifc_odp_per_transport_service_cap_bits {
        u8         receive[0x1];
        u8         write[0x1];
        u8         read[0x1];
-       u8         reserved_at_4[0x1];
+       u8         atomic[0x1];
        u8         srq_receive[0x1];
        u8         reserved_at_6[0x1a];
 };
@@ -782,11 +782,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         log_max_eq[0x4];
 
        u8         max_indirection[0x8];
-       u8         reserved_at_108[0x1];
+       u8         fixed_buffer_size[0x1];
        u8         log_max_mrw_sz[0x7];
        u8         reserved_at_110[0x2];
        u8         log_max_bsf_list_size[0x6];
-       u8         reserved_at_118[0x2];
+       u8         umr_extended_translation_offset[0x1];
+       u8         null_mkey[0x1];
        u8         log_max_klm_list_size[0x6];
 
        u8         reserved_at_120[0xa];
@@ -826,9 +827,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_1a9[0x2];
        u8         local_ca_ack_delay[0x5];
        u8         port_module_event[0x1];
-       u8         reserved_at_1b0[0x1];
+       u8         reserved_at_1b1[0x1];
        u8         ports_check[0x1];
-       u8         reserved_at_1b2[0x1];
+       u8         reserved_at_1b3[0x1];
        u8         disable_link_up[0x1];
        u8         beacon_led[0x1];
        u8         port_type[0x2];
@@ -858,7 +859,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 
        u8         compact_address_vector[0x1];
        u8         striding_rq[0x1];
-       u8         reserved_at_201[0x2];
+       u8         reserved_at_202[0x2];
        u8         ipoib_basic_offloads[0x1];
        u8         reserved_at_205[0xa];
        u8         drain_sigerr[0x1];
@@ -904,7 +905,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         uc[0x1];
        u8         rc[0x1];
 
-       u8         reserved_at_240[0xa];
+       u8         uar_4k[0x1];
+       u8         reserved_at_241[0x9];
        u8         uar_sz[0x6];
        u8         reserved_at_250[0x8];
        u8         log_pg_sz[0x8];
@@ -996,7 +998,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         device_frequency_mhz[0x20];
        u8         device_frequency_khz[0x20];
 
-       u8         reserved_at_500[0x80];
+       u8         reserved_at_500[0x20];
+       u8         num_of_uars_per_page[0x20];
+       u8         reserved_at_540[0x40];
 
        u8         reserved_at_580[0x3f];
        u8         cqe_compression[0x1];
@@ -1009,10 +1013,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         rndv_offload_rc[0x1];
        u8         rndv_offload_dc[0x1];
        u8         log_tag_matching_list_sz[0x5];
-       u8         reserved_at_5e8[0x3];
+       u8         reserved_at_5f8[0x3];
        u8         log_max_xrq[0x5];
 
-       u8         reserved_at_5f0[0x200];
+       u8         reserved_at_600[0x200];
 };
 
 enum mlx5_flow_destination_type {
@@ -2569,6 +2573,7 @@ enum {
        MLX5_MKC_ACCESS_MODE_PA    = 0x0,
        MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
        MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
+       MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
 };
 
 struct mlx5_ifc_mkc_bits {
@@ -3677,6 +3682,10 @@ struct mlx5_ifc_query_special_contexts_out_bits {
        u8         dump_fill_mkey[0x20];
 
        u8         resd_lkey[0x20];
+
+       u8         null_mkey[0x20];
+
+       u8         reserved_at_a0[0x60];
 };
 
 struct mlx5_ifc_query_special_contexts_in_bits {
@@ -4769,12 +4778,11 @@ struct mlx5_ifc_page_fault_resume_in_bits {
 
        u8         error[0x1];
        u8         reserved_at_41[0x4];
-       u8         rdma[0x1];
-       u8         read_write[0x1];
-       u8         req_res[0x1];
-       u8         qpn[0x18];
+       u8         page_fault_type[0x3];
+       u8         wq_number[0x18];
 
-       u8         reserved_at_60[0x20];
+       u8         reserved_at_60[0x8];
+       u8         token[0x18];
 };
 
 struct mlx5_ifc_nop_out_bits {