Merge tag 'mlx5-updates-2021-05-26' of git://git.kernel.org/pub/scm/linux/kernel...

[linux-block.git] / include / linux / mlx5 / driver.h

diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 53b89631a1d9dbbdcf6ce7d676699a377b00a03b..f90f84061438e9ffed21f9e52a235f9c745e7983 100644 (file)
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -127,6 +127,7 @@ enum {
        MLX5_REG_PELC            = 0x500e,
        MLX5_REG_PVLC            = 0x500f,
        MLX5_REG_PCMR            = 0x5041,
+       MLX5_REG_PDDR            = 0x5031,
        MLX5_REG_PMLP            = 0x5002,
        MLX5_REG_PPLM            = 0x5023,
        MLX5_REG_PCAM            = 0x507f,
@@ -438,7 +439,6 @@ struct mlx5_core_health {
        unsigned long                   flags;
        struct work_struct              fatal_report_work;
        struct work_struct              report_work;
-       struct delayed_work             recover_work;
        struct devlink_health_reporter *fw_reporter;
        struct devlink_health_reporter *fw_fatal_reporter;
 };
@@ -517,8 +517,8 @@ struct mlx5_rate_limit {
 
 struct mlx5_rl_entry {
        u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
-       u16 index;
        u64 refcount;
+       u16 index;
        u16 uid;
        u8 dedicated : 1;
 };
@@ -530,6 +530,7 @@ struct mlx5_rl_table {
        u32                     max_rate;
        u32                     min_rate;
        struct mlx5_rl_entry   *rl_entry;
+       u64 refcount;
 };
 
 struct mlx5_core_roce {
@@ -549,6 +550,7 @@ struct mlx5_adev {
        int idx;
 };
 
+struct mlx5_ft_pool;
 struct mlx5_priv {
        /* IRQ table valid only for real pci devices PF or VF */
        struct mlx5_irq_table   *irq_table;
@@ -601,6 +603,7 @@ struct mlx5_priv {
        struct mlx5_core_roce   roce;
        struct mlx5_fc_stats            fc_stats;
        struct mlx5_rl_table            rl_table;
+       struct mlx5_ft_pool             *ft_pool;
 
        struct mlx5_bfreg_data          bfregs;
        struct mlx5_uars_page          *uar;
@@ -644,10 +647,14 @@ struct mlx5_td {
 };
 
 struct mlx5e_resources {
-       u32                        pdn;
-       struct mlx5_td             td;
-       struct mlx5_core_mkey      mkey;
-       struct mlx5_sq_bfreg       bfreg;
+       struct mlx5e_hw_objs {
+               u32                        pdn;
+               struct mlx5_td             td;
+               struct mlx5_core_mkey      mkey;
+               struct mlx5_sq_bfreg       bfreg;
+       } hw_objs;
+       struct devlink_port dl_port;
+       struct net_device *uplink_netdev;
 };
 
 enum mlx5_sw_icm_type {
@@ -698,6 +705,27 @@ struct mlx5_hv_vhca;
 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
 
+enum {
+       MLX5_PROF_MASK_QP_SIZE          = (u64)1 << 0,
+       MLX5_PROF_MASK_MR_CACHE         = (u64)1 << 1,
+};
+
+enum {
+       MR_CACHE_LAST_STD_ENTRY = 20,
+       MLX5_IMR_MTT_CACHE_ENTRY,
+       MLX5_IMR_KSM_CACHE_ENTRY,
+       MAX_MR_CACHE_ENTRIES
+};
+
+struct mlx5_profile {
+       u64     mask;
+       u8      log_max_qp;
+       struct {
+               int     size;
+               int     limit;
+       } mr_cache[MAX_MR_CACHE_ENTRIES];
+};
+
 struct mlx5_core_dev {
        struct device *device;
        enum mlx5_coredev_type coredev_type;
@@ -726,7 +754,7 @@ struct mlx5_core_dev {
        struct mutex            intf_state_mutex;
        unsigned long           intf_state;
        struct mlx5_priv        priv;
-       struct mlx5_profile     *profile;
+       struct mlx5_profile     profile;
        u32                     issi;
        struct mlx5e_resources  mlx5e_res;
        struct mlx5_dm          *dm;
@@ -874,6 +902,11 @@ static inline u32 mlx5_base_mkey(const u32 key)
        return key & 0xffffff00u;
 }
 
+static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
+{
+       return ((u32)1 << log_sz) << log_stride;
+}
+
 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
                                        u8 log_stride, u8 log_sz,
                                        u16 strides_offset,
@@ -1073,18 +1106,6 @@ static inline u8 mlx5_mkey_variant(u32 mkey)
        return mkey & 0xff;
 }
 
-enum {
-       MLX5_PROF_MASK_QP_SIZE          = (u64)1 << 0,
-       MLX5_PROF_MASK_MR_CACHE         = (u64)1 << 1,
-};
-
-enum {
-       MR_CACHE_LAST_STD_ENTRY = 20,
-       MLX5_IMR_MTT_CACHE_ENTRY,
-       MLX5_IMR_KSM_CACHE_ENTRY,
-       MAX_MR_CACHE_ENTRIES
-};
-
 /* Async-atomic event notifier used by mlx5 core to forward FW
  * evetns recived from event queue to mlx5 consumers.
  * Optimise event queue dipatching.
@@ -1138,15 +1159,6 @@ int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
                            struct ib_device *device,
                            struct rdma_netdev_alloc_params *params);
 
-struct mlx5_profile {
-       u64     mask;
-       u8      log_max_qp;
-       struct {
-               int     size;
-               int     limit;
-       } mr_cache[MAX_MR_CACHE_ENTRIES];
-};
-
 enum {
        MLX5_PCI_DEV_IS_VF              = 1 << 0,
 };
@@ -1226,7 +1238,7 @@ enum {
        MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
 };
 
-static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
+static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)
 {
        struct devlink *devlink = priv_to_devlink(dev);
        union devlink_param_value val;