IB/mlx5: Fill XRQ capabilities

[linux-2.6-block.git] / include / linux / mlx5 / driver.h

diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 93273d9ea4d145f125846f0c9a56a5a6e74915e4..99d88624ad0710d8e4e63a6d9d805a6a8239f988 100644 (file)
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -44,6 +44,7 @@
 #include <linux/workqueue.h>
 #include <linux/mempool.h>
 #include <linux/interrupt.h>
+#include <linux/idr.h>
 
 #include <linux/mlx5/device.h>
 #include <linux/mlx5/doorbell.h>
@@ -108,6 +109,9 @@ enum {
        MLX5_REG_QTCT            = 0x400a,
        MLX5_REG_DCBX_PARAM      = 0x4020,
        MLX5_REG_DCBX_APP        = 0x4021,
+       MLX5_REG_FPGA_CAP        = 0x4022,
+       MLX5_REG_FPGA_CTRL       = 0x4023,
+       MLX5_REG_FPGA_ACCESS_REG = 0x4024,
        MLX5_REG_PCAP            = 0x5001,
        MLX5_REG_PMTU            = 0x5003,
        MLX5_REG_PTYS            = 0x5004,
@@ -129,6 +133,9 @@ enum {
        MLX5_REG_MPCNT           = 0x9051,
        MLX5_REG_MTPPS           = 0x9053,
        MLX5_REG_MTPPSE          = 0x9054,
+       MLX5_REG_MCQI            = 0x9061,
+       MLX5_REG_MCC             = 0x9062,
+       MLX5_REG_MCDA            = 0x9063,
        MLX5_REG_MCAM            = 0x907f,
 };
 
@@ -155,6 +162,13 @@ enum dbg_rsc_type {
        MLX5_DBG_RSC_CQ,
 };
 
+enum port_state_policy {
+       MLX5_POLICY_DOWN        = 0,
+       MLX5_POLICY_UP          = 1,
+       MLX5_POLICY_FOLLOW      = 2,
+       MLX5_POLICY_INVALID     = 0xffffffff
+};
+
 struct mlx5_field_desc {
        struct dentry          *dent;
        int                     i;
@@ -178,6 +192,7 @@ enum mlx5_dev_event {
        MLX5_DEV_EVENT_GUID_CHANGE,
        MLX5_DEV_EVENT_CLIENT_REREG,
        MLX5_DEV_EVENT_PPS,
+       MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
 };
 
 enum mlx5_port_status {
@@ -284,7 +299,7 @@ struct mlx5_cmd {
        struct semaphore pages_sem;
        int     mode;
        struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
-       struct pci_pool *pool;
+       struct dma_pool *pool;
        struct mlx5_cmd_debug dbg;
        struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
        int checksum_disabled;
@@ -518,6 +533,9 @@ struct mlx5_mkey_table {
 
 struct mlx5_vf_context {
        int     enabled;
+       u64     port_guid;
+       u64     node_guid;
+       enum port_state_policy  policy;
 };
 
 struct mlx5_core_sriov {
@@ -527,7 +545,6 @@ struct mlx5_core_sriov {
 };
 
 struct mlx5_irq_info {
-       cpumask_var_t mask;
        char name[MLX5_MAX_IRQ_NAME];
 };
 
@@ -590,7 +607,6 @@ struct mlx5_port_module_event_stats {
 struct mlx5_priv {
        char                    name[MLX5_MAX_NAME_LEN];
        struct mlx5_eq_table    eq_table;
-       struct msix_entry       *msix_arr;
        struct mlx5_irq_info    *irq_info;
 
        /* pages stuff */
@@ -732,6 +748,14 @@ struct mlx5e_resources {
        struct mlx5_sq_bfreg       bfreg;
 };
 
+#define MLX5_MAX_RESERVED_GIDS 8
+
+struct mlx5_rsvd_gids {
+       unsigned int start;
+       unsigned int count;
+       struct ida ida;
+};
+
 struct mlx5_core_dev {
        struct pci_dev         *pdev;
        /* sync pci state */
@@ -761,6 +785,13 @@ struct mlx5_core_dev {
        atomic_t                num_qps;
        u32                     issi;
        struct mlx5e_resources  mlx5e_res;
+       struct {
+               struct mlx5_rsvd_gids   reserved_gids;
+               atomic_t                roce_en;
+       } roce;
+#ifdef CONFIG_MLX5_FPGA
+       struct mlx5_fpga_device *fpga;
+#endif
 #ifdef CONFIG_RFS_ACCEL
        struct cpu_rmap         *rmap;
 #endif
@@ -812,6 +843,7 @@ struct mlx5_cmd_work_ent {
        u64                     ts1;
        u64                     ts2;
        u16                     op;
+       bool                    polling;
 };
 
 struct mlx5_pas {
@@ -819,13 +851,6 @@ struct mlx5_pas {
        u8      log_sz;
 };
 
-enum port_state_policy {
-       MLX5_POLICY_DOWN        = 0,
-       MLX5_POLICY_UP          = 1,
-       MLX5_POLICY_FOLLOW      = 2,
-       MLX5_POLICY_INVALID     = 0xffffffff
-};
-
 enum phy_port_state {
        MLX5_AAA_111
 };
@@ -895,11 +920,6 @@ static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
        return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
 }
 
-static inline void *mlx5_vzalloc(unsigned long size)
-{
-       return kvzalloc(size, GFP_KERNEL);
-}
-
 static inline u32 mlx5_base_mkey(const u32 key)
 {
        return key & 0xffffff00u;
@@ -915,6 +935,8 @@ int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
                     void *out, int out_size, mlx5_cmd_cbk_t callback,
                     void *context);
+int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
+                         void *out, int out_size);
 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
 
 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
@@ -925,6 +947,8 @@ int mlx5_health_init(struct mlx5_core_dev *dev);
 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
+void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
+void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
                        struct mlx5_buf *buf, int node);
 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
@@ -1038,6 +1062,11 @@ int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
                     bool map_wc, bool fast_path);
 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
 
+unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
+int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
+                          u8 roce_version, u8 roce_l3_type, const u8 *gid,
+                          const u8 *mac, bool vlan, u16 vlan_id);
+
 static inline int fw_initializing(struct mlx5_core_dev *dev)
 {
        return ioread32be(&dev->iseg->initializing) >> 31;
@@ -1064,7 +1093,7 @@ enum {
 };
 
 enum {
-       MAX_UMR_CACHE_ENTRY = 20,
+       MR_CACHE_LAST_STD_ENTRY = 20,
        MLX5_IMR_MTT_CACHE_ENTRY,
        MLX5_IMR_KSM_CACHE_ENTRY,
        MAX_MR_CACHE_ENTRIES
@@ -1158,4 +1187,10 @@ enum {
        MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
 };
 
+static inline const struct cpumask *
+mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
+{
+       return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector);
+}
+
 #endif /* MLX5_DRIVER_H */