#include <linux/regulator/consumer.h>
#include <linux/string.h>
#include <linux/of.h>
+#include <linux/clk.h>
#include <video/omapdss.h>
struct platform_device *pdev;
struct regulator *vdds_dsi_reg;
- struct platform_device *dsidev;
+ struct dss_pll *pll;
struct mutex lock;
return dev_get_drvdata(&pdev->dev);
}
-static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
+static struct dss_pll *dpi_get_pll(enum omap_channel channel)
{
/*
* XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
case OMAPDSS_VER_OMAP4:
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
- return dsi_get_dsidev_from_id(0);
+ return dss_pll_find("dsi0");
case OMAP_DSS_CHANNEL_LCD2:
- return dsi_get_dsidev_from_id(1);
+ return dss_pll_find("dsi1");
default:
return NULL;
}
case OMAPDSS_VER_OMAP5:
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
- return dsi_get_dsidev_from_id(0);
+ return dss_pll_find("dsi0");
case OMAP_DSS_CHANNEL_LCD3:
- return dsi_get_dsidev_from_id(1);
+ return dss_pll_find("dsi1");
default:
return NULL;
}
}
struct dpi_clk_calc_ctx {
- struct platform_device *dsidev;
+ struct dss_pll *pll;
/* inputs */
/* outputs */
- struct dsi_clock_info dsi_cinfo;
+ struct dss_pll_clock_info dsi_cinfo;
unsigned long fck;
struct dispc_clock_info dispc_cinfo;
};
}
-static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
+static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
* shifted. So skip all odd dividers when the pixel clock is on the
* higher side.
*/
- if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000)
+ if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000)
return false;
- ctx->dsi_cinfo.regm_hsdiv[HSDIV_DISPC] = regm_dispc;
+ ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
}
-static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
- unsigned long pll,
+static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
+ unsigned long clkdco,
void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
- ctx->dsi_cinfo.regn = regn;
- ctx->dsi_cinfo.regm = regm;
+ ctx->dsi_cinfo.n = n;
+ ctx->dsi_cinfo.m = m;
ctx->dsi_cinfo.fint = fint;
- ctx->dsi_cinfo.clkdco = pll;
+ ctx->dsi_cinfo.clkdco = clkdco;
- return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
- dpi_calc_hsdiv_cb, ctx);
+ return dss_pll_hsdiv_calc(ctx->pll, clkdco,
+ ctx->pck_min, dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
+ dpi_calc_hsdiv_cb, ctx);
}
static bool dpi_calc_dss_cb(unsigned long fck, void *data)
unsigned long clkin;
unsigned long pll_min, pll_max;
- clkin = dsi_get_pll_clkin(dpi->dsidev);
-
memset(ctx, 0, sizeof(*ctx));
- ctx->dsidev = dpi->dsidev;
+ ctx->pll = dpi->pll;
ctx->pck_min = pck - 1000;
ctx->pck_max = pck + 1000;
pll_min = 0;
pll_max = 0;
- return dsi_pll_calc(dpi->dsidev, clkin,
+ clkin = clk_get_rate(ctx->pll->clkin);
+
+ return dss_pll_calc(ctx->pll, clkin,
pll_min, pll_max,
dpi_calc_pll_cb, ctx);
}
if (!ok)
return -EINVAL;
- r = dsi_pll_set_clock_div(dpi->dsidev, &ctx.dsi_cinfo);
+ r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo);
if (r)
return r;
unsigned long pck;
int r = 0;
- if (dpi->dsidev)
+ if (dpi->pll)
r = dpi_set_dsi_clk(dpi, mgr->id, t->pixelclock, &fck,
&lck_div, &pck_div);
else
if (r)
goto err_src_sel;
- if (dpi->dsidev) {
- r = dsi_pll_init(dpi->dsidev);
+ if (dpi->pll) {
+ r = dss_pll_enable(dpi->pll);
if (r)
goto err_dsi_pll_init;
}
err_mgr_enable:
err_set_mode:
- if (dpi->dsidev)
- dsi_pll_uninit(dpi->dsidev, true);
+ if (dpi->pll)
+ dss_pll_disable(dpi->pll);
err_dsi_pll_init:
err_src_sel:
dispc_runtime_put();
dss_mgr_disable(mgr);
- if (dpi->dsidev) {
+ if (dpi->pll) {
dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
- dsi_pll_uninit(dpi->dsidev, true);
+ dss_pll_disable(dpi->pll);
}
dispc_runtime_put();
if (timings->pixelclock == 0)
return -EINVAL;
- if (dpi->dsidev) {
+ if (dpi->pll) {
ok = dpi_dsi_clk_calc(dpi, timings->pixelclock, &ctx);
if (!ok)
return -EINVAL;
mutex_unlock(&dpi->lock);
}
-static int dpi_verify_dsi_pll(struct platform_device *dsidev)
+static int dpi_verify_dsi_pll(struct dss_pll *pll)
{
int r;
/* do initial setup with the PLL to see if it is operational */
- r = dsi_pll_init(dsidev);
+ r = dss_pll_enable(pll);
if (r)
return r;
- dsi_pll_uninit(dsidev, true);
+ dss_pll_disable(pll);
return 0;
}
static void dpi_init_pll(struct dpi_data *dpi)
{
- struct platform_device *dsidev;
+ struct dss_pll *pll;
- if (dpi->dsidev)
+ if (dpi->pll)
return;
- dsidev = dpi_get_dsidev(dpi->output.dispc_channel);
- if (!dsidev)
+ pll = dpi_get_pll(dpi->output.dispc_channel);
+ if (!pll)
return;
- if (dpi_verify_dsi_pll(dsidev)) {
+ if (dpi_verify_dsi_pll(pll)) {
DSSWARN("DSI PLL not operational\n");
return;
}
- dpi->dsidev = dsidev;
+ dpi->pll = pll;
}
/*