#endif
#define TIMER_BASE 25 /* 40MHz master clock */
-#define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow aquisition, maybe I'll support this someday */
+#define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
#define DMA_BUFFER_SIZE 0x1000
#define PCI_VENDOR_ID_COMPUTERBOARDS 0x1307
ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, /* upper 8 bits of delay interval counter */
ADC_COUNT_LOWER_REG = 0x1e, /* lower 16 bits of hardware conversion/scan counter */
ADC_COUNT_UPPER_REG = 0x20, /* upper 8 bits of hardware conversion/scan counter */
- ADC_START_REG = 0x22, /* software trigger to start aquisition */
+ ADC_START_REG = 0x22, /* software trigger to start acquisition */
ADC_CONVERT_REG = 0x24, /* initiates single conversion */
ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */
EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
- EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc aquisition done interrupt */
+ EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done interrupt */
DAC_INTR_SRC_MASK = 0x30,
DAC_INTR_QEMPTY_BITS = 0x0,
DAC_INTR_HIGH_CHAN_BITS = 0x10,
spin_unlock_irqrestore(&dev->spinlock, flags);
- /* start aquisition */
+ /* start acquisition */
if (cmd->start_src == TRIG_NOW) {
writew(0, priv(dev)->main_iobase + ADC_START_REG);
DEBUG_PRINT("soft trig\n");
/* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
* The pci-4020 hardware only supports
* dma transfers (it only supports the use of pio for draining the last remaining
- * points from the fifo when a data aquisition operation has completed).
+ * points from the fifo when a data acquisition operation has completed).
*/
static void pio_drain_ai_fifo_32(struct comedi_device *dev)
{
comedi_error(dev, "fifo overrun");
async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
}
- /* spin lock makes sure noone else changes plx dma control reg */
+ /* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
async = s->async;
cmd = &async->cmd;
- /* spin lock makes sure noone else changes plx dma control reg */
+ /* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */