}
/*
- * Sequencer Interupt Status
+ * Sequencer Interrupt Status
*/
register SEQINTSTAT {
address 0x00C
}
/*
- * CMC Recieve Message 0
+ * CMC Receive Message 0
*/
register CMCRXMSG0 {
address 0x090
}
/*
- * Overlay Recieve Message 0
+ * Overlay Receive Message 0
*/
register OVLYRXMSG0 {
address 0x090
}
/*
- * CMC Recieve Message 1
+ * CMC Receive Message 1
*/
register CMCRXMSG1 {
address 0x091
}
/*
- * Overlay Recieve Message 1
+ * Overlay Receive Message 1
*/
register OVLYRXMSG1 {
address 0x091
}
/*
- * CMC Recieve Message 2
+ * CMC Receive Message 2
*/
register CMCRXMSG2 {
address 0x092
}
/*
- * Overlay Recieve Message 2
+ * Overlay Receive Message 2
*/
register OVLYRXMSG2 {
address 0x092
}
/*
- * CMC Recieve Message 3
+ * CMC Receive Message 3
*/
register CMCRXMSG3 {
address 0x093
}
/*
- * Overlay Recieve Message 3
+ * Overlay Receive Message 3
*/
register OVLYRXMSG3 {
address 0x093
/*
* LQ Packet In
- * The last LQ Packet recieved
+ * The last LQ Packet received
*/
register LQIN {
address 0x020
}
/*
- * Shaddow Host Address.
+ * Shadow Host Address.
*/
register SHADDR {
address 0x060
/*
* The maximum amount of time to wait, when interrupt coalescing
- * is enabled, before issueing a CMDCMPLT interrupt for a completed
+ * is enabled, before issuing a CMDCMPLT interrupt for a completed
* command.
*/
INT_COALESCING_TIMER {