Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...

[linux-2.6-block.git] / drivers / pinctrl / intel / pinctrl-cherryview.c

diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index cfb7168fe76683e044ea9db88c5dcac331477261..aae51c507f590e77c854a3547779995ea227e7e4 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1543,6 +1543,30 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
        {}
 };
 
+static void chv_init_irq_valid_mask(struct gpio_chip *chip,
+                                   unsigned long *valid_mask,
+                                   unsigned int ngpios)
+{
+       struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
+       const struct chv_community *community = pctrl->community;
+       int i;
+
+       /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
+       for (i = 0; i < community->npins; i++) {
+               const struct pinctrl_pin_desc *desc;
+               u32 intsel;
+
+               desc = &community->pins[i];
+
+               intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
+               intsel &= CHV_PADCTRL0_INTSEL_MASK;
+               intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
+
+               if (intsel >= community->nirqs)
+                       clear_bit(i, valid_mask);
+       }
+}
+
 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
 {
        const struct chv_gpio_pinrange *range;
@@ -1557,7 +1581,8 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
        chip->label = dev_name(pctrl->dev);
        chip->parent = pctrl->dev;
        chip->base = -1;
-       chip->irq.need_valid_mask = need_valid_mask;
+       if (need_valid_mask)
+               chip->irq.init_valid_mask = chv_init_irq_valid_mask;
 
        ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
        if (ret) {
@@ -1576,21 +1601,6 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
                }
        }
 
-       /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
-       for (i = 0; i < community->npins; i++) {
-               const struct pinctrl_pin_desc *desc;
-               u32 intsel;
-
-               desc = &community->pins[i];
-
-               intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
-               intsel &= CHV_PADCTRL0_INTSEL_MASK;
-               intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
-
-               if (need_valid_mask && intsel >= community->nirqs)
-                       clear_bit(i, chip->irq.valid_mask);
-       }
-
        /*
         * The same set of machines in chv_no_valid_mask[] have incorrectly
         * configured GPIOs that generate spurious interrupts so we use