Merge branch 'remotes/lorenzo/pci/bridge-emul'

[linux-2.6-block.git] / drivers / pci / pci-bridge-emul.c

diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 0d1177e52a43b96609a64e0b39eab9f6f78be01f..c994ebec2360387755bde3ba5456c6a948a2d587 100644 (file)
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -139,8 +139,13 @@ struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
                .ro = GENMASK(7, 0),
        },
 
+       /*
+        * If expansion ROM is unsupported then ROM Base Address register must
+        * be implemented as read-only register that return 0 when read, same
+        * as for unused Base Address registers.
+        */
        [PCI_ROM_ADDRESS1 / 4] = {
-               .rw = GENMASK(31, 11) | BIT(0),
+               .ro = ~0,
        },
 
        /*
@@ -171,41 +176,55 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
        [PCI_CAP_LIST_ID / 4] = {
                /*
                 * Capability ID, Next Capability Pointer and
-                * Capabilities register are all read-only.
+                * bits [14:0] of Capabilities register are all read-only.
+                * Bit 15 of Capabilities register is reserved.
                 */
-               .ro = ~0,
+               .ro = GENMASK(30, 0),
        },
 
        [PCI_EXP_DEVCAP / 4] = {
-               .ro = ~0,
+               /*
+                * Bits [31:29] and [17:16] are reserved.
+                * Bits [27:18] are reserved for non-upstream ports.
+                * Bits 28 and [14:6] are reserved for non-endpoint devices.
+                * Other bits are read-only.
+                */
+               .ro = BIT(15) | GENMASK(5, 0),
        },
 
        [PCI_EXP_DEVCTL / 4] = {
-               /* Device control register is RW */
-               .rw = GENMASK(15, 0),
+               /*
+                * Device control register is RW, except bit 15 which is
+                * reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
+                */
+               .rw = GENMASK(14, 0),
 
                /*
                 * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
-                * the rest is reserved
+                * the rest is reserved. Also bit 6 is reserved for non-upstream
+                * ports.
                 */
-               .w1c = (BIT(6) | GENMASK(3, 0)) << 16,
+               .w1c = GENMASK(3, 0) << 16,
                .ro = GENMASK(5, 4) << 16,
        },
 
        [PCI_EXP_LNKCAP / 4] = {
-               /* All bits are RO, except bit 23 which is reserved */
-               .ro = lower_32_bits(~BIT(23)),
+               /*
+                * All bits are RO, except bit 23 which is reserved and
+                * bit 18 which is reserved for non-upstream ports.
+                */
+               .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
        },
 
        [PCI_EXP_LNKCTL / 4] = {
                /*
                 * Link control has bits [15:14], [11:3] and [1:0] RW, the
-                * rest is reserved.
+                * rest is reserved. Bit 8 is reserved for non-upstream ports.
                 *
                 * Link status has bits [13:0] RO, and bits [15:14]
                 * W1C.
                 */
-               .rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0),
+               .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
                .ro = GENMASK(13, 0) << 16,
                .w1c = GENMASK(15, 14) << 16,
        },
@@ -324,11 +343,9 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
 
        if (bridge->has_pcie) {
                bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
+               bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
                bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
-               /* Set PCIe v2, root port, slot support */
-               bridge->pcie_conf.cap =
-                       cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
-                                   PCI_EXP_FLAGS_SLOT);
+               bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
                bridge->pcie_cap_regs_behavior =
                        kmemdup(pcie_cap_regs_behavior,
                                sizeof(pcie_cap_regs_behavior),
@@ -337,6 +354,27 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
                        kfree(bridge->pci_regs_behavior);
                        return -ENOMEM;
                }
+               /* These bits are applicable only for PCI and reserved on PCIe */
+               bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
+                       ~GENMASK(15, 8);
+               bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
+                       ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
+                          PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
+                          PCI_COMMAND_FAST_BACK) |
+                         (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
+                          PCI_STATUS_DEVSEL_MASK) << 16);
+               bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
+                       ~GENMASK(31, 24);
+               bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
+                       ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
+                          PCI_STATUS_DEVSEL_MASK) << 16);
+               bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
+                       ~((PCI_BRIDGE_CTL_MASTER_ABORT |
+                          BIT(8) | BIT(9) | BIT(11)) << 16);
+               bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
+                       ~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
+               bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
+                       ~(BIT(10) << 16);
        }
 
        if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {