ntb: Adding Skylake Xeon NTB support

[linux-2.6-block.git] / drivers / ntb / hw / intel / ntb_hw_intel.h

diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
index 3ec149cf656276dd362fad25b37661b69d5fb3d0..6e8c1824eb19e6d5a30f121272fa18a9b446b51e 100644 (file)
--- a/drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
@@ -70,6 +70,7 @@
 #define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX        0x6F0D
 #define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
 #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
+#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX        0x201C
 
 /* Intel Xeon hardware */
 
@@ -150,6 +151,51 @@
 #define XEON_DB_TOTAL_SHIFT            16
 #define XEON_SPAD_COUNT                        16
 
+/* Intel Skylake Xeon hardware */
+#define SKX_IMBAR1SZ_OFFSET            0x00d1
+#define SKX_IMBAR2SZ_OFFSET            0x00d5
+#define SKX_EMBAR1SZ_OFFSET            0x00d3
+#define SKX_EMBAR2SZ_OFFSET            0x00d6
+#define SKX_DEVCTRL_OFFSET             0x0098
+#define SKX_DEVSTS_OFFSET              0x009a
+#define SKX_UNCERRSTS_OFFSET           0x014c
+#define SKX_CORERRSTS_OFFSET           0x0158
+#define SKX_LINK_STATUS_OFFSET         0x01a2
+
+#define SKX_NTBCNTL_OFFSET             0x0000
+#define SKX_IMBAR1XBASE_OFFSET         0x0010          /* SBAR2XLAT */
+#define SKX_IMBAR1XLMT_OFFSET          0x0018          /* SBAR2LMT */
+#define SKX_IMBAR2XBASE_OFFSET         0x0020          /* SBAR4XLAT */
+#define SKX_IMBAR2XLMT_OFFSET          0x0028          /* SBAR4LMT */
+#define SKX_IM_INT_STATUS_OFFSET       0x0040
+#define SKX_IM_INT_DISABLE_OFFSET      0x0048
+#define SKX_IM_SPAD_OFFSET             0x0080          /* SPAD */
+#define SKX_USMEMMISS_OFFSET           0x0070
+#define SKX_INTVEC_OFFSET              0x00d0
+#define SKX_IM_DOORBELL_OFFSET         0x0100          /* SDOORBELL0 */
+#define SKX_B2B_SPAD_OFFSET            0x0180          /* B2B SPAD */
+#define SKX_EMBAR0XBASE_OFFSET         0x4008          /* B2B_XLAT */
+#define SKX_EMBAR1XBASE_OFFSET         0x4010          /* PBAR2XLAT */
+#define SKX_EMBAR1XLMT_OFFSET          0x4018          /* PBAR2LMT */
+#define SKX_EMBAR2XBASE_OFFSET         0x4020          /* PBAR4XLAT */
+#define SKX_EMBAR2XLMT_OFFSET          0x4028          /* PBAR4LMT */
+#define SKX_EM_INT_STATUS_OFFSET       0x4040
+#define SKX_EM_INT_DISABLE_OFFSET      0x4048
+#define SKX_EM_SPAD_OFFSET             0x4080          /* remote SPAD */
+#define SKX_EM_DOORBELL_OFFSET         0x4100          /* PDOORBELL0 */
+#define SKX_SPCICMD_OFFSET             0x4504          /* SPCICMD */
+#define SKX_EMBAR0_OFFSET              0x4510          /* SBAR0BASE */
+#define SKX_EMBAR1_OFFSET              0x4518          /* SBAR23BASE */
+#define SKX_EMBAR2_OFFSET              0x4520          /* SBAR45BASE */
+
+#define SKX_DB_COUNT                   32
+#define SKX_DB_LINK                    32
+#define SKX_DB_LINK_BIT                        BIT_ULL(SKX_DB_LINK)
+#define SKX_DB_MSIX_VECTOR_COUNT       33
+#define SKX_DB_MSIX_VECTOR_SHIFT       1
+#define SKX_DB_TOTAL_SHIFT             33
+#define SKX_SPAD_COUNT                 16
+
 /* Intel Atom hardware */
 
 #define ATOM_SBAR2XLAT_OFFSET          0x0008
@@ -240,6 +286,7 @@
 #define NTB_HWERR_SDOORBELL_LOCKUP     BIT_ULL(0)
 #define NTB_HWERR_SB01BASE_LOCKUP      BIT_ULL(1)
 #define NTB_HWERR_B2BDOORBELL_BIT14    BIT_ULL(2)
+#define NTB_HWERR_MSIX_VECTOR32_BAD    BIT_ULL(3)
 
 /* flags to indicate unsafe api */
 #define NTB_UNSAFE_DB                  BIT_ULL(0)
@@ -263,6 +310,7 @@ struct intel_ntb_reg {
 struct intel_ntb_alt_reg {
        unsigned long                   db_bell;
        unsigned long                   db_mask;
+       unsigned long                   db_clear;
        unsigned long                   spad;
 };