#define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
#define NUM_PKT_BUF 64
#define NUM_BUFPOOL 32
-#define START_ETH_BUFNUM 2
-#define START_BP_BUFNUM 0x22
-#define START_RING_NUM 8
+
+#define START_CPU_BUFNUM_0 0
+#define START_ETH_BUFNUM_0 2
+#define START_BP_BUFNUM_0 0x22
+#define START_RING_NUM_0 8
+#define START_CPU_BUFNUM_1 12
+#define START_ETH_BUFNUM_1 10
+#define START_BP_BUFNUM_1 0x2A
+#define START_RING_NUM_1 264
#define PHY_POLL_LINK_ON (10 * HZ)
#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
struct xgene_mac_ops *mac_ops;
struct xgene_port_ops *port_ops;
struct delayed_work link_work;
+ u32 port_id;
+ u8 cpu_bufnum;
+ u8 eth_bufnum;
+ u8 bp_bufnum;
+ u16 ring_num;
};
struct xgene_indirect_ctl {