/*******************************************************************************
Intel PRO/1000 Linux driver
- Copyright(c) 1999 - 2007 Intel Corporation.
+ Copyright(c) 1999 - 2008 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
#define E1000_FACTPS_MNGCG 0x20000000
-#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management
- * Technology signature */
+/* Intel(R) Active Management Technology signature */
+#define E1000_IAMT_SIGNATURE 0x544D4149
/**
* e1000e_get_bus_info_pcie - Get PCIe bus information
{
u32 rar_low, rar_high;
- /* HW expects these in little endian so we reverse the byte order
+ /*
+ * HW expects these in little endian so we reverse the byte order
* from network order (big endian) to little endian
*/
rar_low = ((u32) addr[0] |
{
u32 hash_bit, hash_reg, mta;
- /* The MTA is a register array of 32-bit registers. It is
+ /*
+ * The MTA is a register array of 32-bit registers. It is
* treated like an array of (32*mta_reg_count) bits. We want to
* set bit BitArray[hash_value]. So we figure out what register
* the bit is in, read it, OR in the new bit, then write
/* Register count multiplied by bits per register */
hash_mask = (hw->mac.mta_reg_count * 32) - 1;
- /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
- * where 0xFF would still fall within the hash mask. */
+ /*
+ * For a mc_filter_type of 0, bit_shift is the number of left-shifts
+ * where 0xFF would still fall within the hash mask.
+ */
while (hash_mask >> bit_shift != 0xFF)
bit_shift++;
- /* The portion of the address that is used for the hash table
+ /*
+ * The portion of the address that is used for the hash table
* is determined by the mc_filter_type setting.
* The algorithm is such that there is a total of 8 bits of shifting.
* The bit_shift for a mc_filter_type of 0 represents the number of
* cases are a variation of this algorithm...essentially raising the
* number of bits to shift mc_addr[5] left, while still keeping the
* 8-bit shifting total.
- */
- /* For example, given the following Destination MAC Address and an
+ *
+ * For example, given the following Destination MAC Address and an
* mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
* we can see that the bit_shift for case 0 is 4. These are the hash
* values resulting from each mc_filter_type...
u32 hash_value;
u32 i;
- /* Load the first set of multicast addresses into the exact
+ /*
+ * Load the first set of multicast addresses into the exact
* filters (RAR). If there are not enough to fill the RAR
* array, clear the filters.
*/
s32 ret_val;
bool link;
- /* We only want to go out to the PHY registers to see if Auto-Neg
+ /*
+ * We only want to go out to the PHY registers to see if Auto-Neg
* has completed and/or if our link status has changed. The
* get_link_status flag is set upon receiving a Link Status
* Change or Rx Sequence Error interrupt.
if (!mac->get_link_status)
return 0;
- /* First we want to see if the MII Status Register reports
+ /*
+ * First we want to see if the MII Status Register reports
* link. If so, then we want to get the current speed/duplex
* of the PHY.
*/
mac->get_link_status = 0;
- /* Check if there was DownShift, must be checked
- * immediately after link-up */
+ /*
+ * Check if there was DownShift, must be checked
+ * immediately after link-up
+ */
e1000e_check_downshift(hw);
- /* If we are forcing speed/duplex, then we simply return since
+ /*
+ * If we are forcing speed/duplex, then we simply return since
* we have already determined whether we have link or not.
*/
if (!mac->autoneg) {
return ret_val;
}
- /* Auto-Neg is enabled. Auto Speed Detection takes care
+ /*
+ * Auto-Neg is enabled. Auto Speed Detection takes care
* of MAC speed/duplex configuration. So we only need to
* configure Collision Distance in the MAC.
*/
e1000e_config_collision_dist(hw);
- /* Configure Flow Control now that Auto-Neg has completed.
+ /*
+ * Configure Flow Control now that Auto-Neg has completed.
* First, we need to restore the desired flow control
* settings because we may have had to re-autoneg with a
* different link partner.
status = er32(STATUS);
rxcw = er32(RXCW);
- /* If we don't have link (auto-negotiation failed or link partner
+ /*
+ * If we don't have link (auto-negotiation failed or link partner
* cannot auto-negotiate), the cable is plugged in (we have signal),
* and our link partner is not trying to auto-negotiate with us (we
* are receiving idles or data), we need to force link up. We also
return ret_val;
}
} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
- /* If we are forcing link and we are receiving /C/ ordered
+ /*
+ * If we are forcing link and we are receiving /C/ ordered
* sets, re-enable auto-negotiation in the TXCW register
* and disable forced link in the Device Control register
* in an attempt to auto-negotiate with our link partner.
status = er32(STATUS);
rxcw = er32(RXCW);
- /* If we don't have link (auto-negotiation failed or link partner
+ /*
+ * If we don't have link (auto-negotiation failed or link partner
* cannot auto-negotiate), and our link partner is not trying to
* auto-negotiate with us (we are receiving idles or data),
* we need to force link up. We also need to give auto-negotiation
return ret_val;
}
} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
- /* If we are forcing link and we are receiving /C/ ordered
+ /*
+ * If we are forcing link and we are receiving /C/ ordered
* sets, re-enable auto-negotiation in the TXCW register
* and disable forced link in the Device Control register
* in an attempt to auto-negotiate with our link partner.
mac->serdes_has_link = 1;
} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
- /* If we force link for non-auto-negotiation switch, check
+ /*
+ * If we force link for non-auto-negotiation switch, check
* link status based on MAC synchronization for internal
* serdes media type.
*/
s32 ret_val;
u16 nvm_data;
- /* Read and store word 0x0F of the EEPROM. This word contains bits
+ /*
+ * Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
* disabling auto-negotiation, and the direction of the
struct e1000_mac_info *mac = &hw->mac;
s32 ret_val;
- /* In the case of the phy reset being blocked, we already have a link.
+ /*
+ * In the case of the phy reset being blocked, we already have a link.
* We do not need to set it up again.
*/
if (e1000_check_reset_block(hw))
return ret_val;
}
- /* We want to save off the original Flow Control configuration just
+ /*
+ * We want to save off the original Flow Control configuration just
* in case we get disconnected and then reconnected into a different
* hub or switch with different Flow Control capabilities.
*/
if (ret_val)
return ret_val;
- /* Initialize the flow control address, type, and PAUSE timer
+ /*
+ * Initialize the flow control address, type, and PAUSE timer
* registers to their default values. This is done even if flow
* control is disabled, because it does not hurt anything to
* initialize these registers.
struct e1000_mac_info *mac = &hw->mac;
u32 txcw;
- /* Check for a software override of the flow control settings, and
+ /*
+ * Check for a software override of the flow control settings, and
* setup the device accordingly. If auto-negotiation is enabled, then
* software will have to set the "PAUSE" bits to the correct value in
* the Transmit Config Word Register (TXCW) and re-start auto-
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but we
* do not support receiving pause frames).
- * 3: Both Rx and TX flow control (symmetric) are enabled.
+ * 3: Both Rx and Tx flow control (symmetric) are enabled.
*/
switch (mac->fc) {
case e1000_fc_none:
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
break;
case e1000_fc_rx_pause:
- /* RX Flow control is enabled and TX Flow control is disabled
+ /*
+ * Rx Flow control is enabled and Tx Flow control is disabled
* by a software over-ride. Since there really isn't a way to
- * advertise that we are capable of RX Pause ONLY, we will
- * advertise that we support both symmetric and asymmetric RX
+ * advertise that we are capable of Rx Pause ONLY, we will
+ * advertise that we support both symmetric and asymmetric Rx
* PAUSE. Later, we will disable the adapter's ability to send
* PAUSE frames.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
break;
case e1000_fc_tx_pause:
- /* TX Flow control is enabled, and RX Flow control is disabled,
+ /*
+ * Tx Flow control is enabled, and Rx Flow control is disabled,
* by a software over-ride.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
break;
case e1000_fc_full:
- /* Flow control (both RX and TX) is enabled by a software
+ /*
+ * Flow control (both Rx and Tx) is enabled by a software
* over-ride.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
u32 i, status;
s32 ret_val;
- /* If we have a signal (the cable is plugged in, or assumed true for
+ /*
+ * If we have a signal (the cable is plugged in, or assumed true for
* serdes media) then poll for a "Link-Up" indication in the Device
* Status Register. Time-out if a link isn't seen in 500 milliseconds
* seconds (Auto-negotiation should complete in less than 500
if (i == FIBER_LINK_UP_LIMIT) {
hw_dbg(hw, "Never got a valid link from auto-neg!!!\n");
mac->autoneg_failed = 1;
- /* AutoNeg failed to achieve a link, so we'll call
+ /*
+ * AutoNeg failed to achieve a link, so we'll call
* mac->check_for_link. This routine will force the
* link up if we detect a signal. This will allow us to
* communicate with non-autonegotiating link partners.
if (ret_val)
return ret_val;
- /* Since auto-negotiation is enabled, take the link out of reset (the
+ /*
+ * Since auto-negotiation is enabled, take the link out of reset (the
* link will be in reset, because we previously reset the chip). This
* will restart auto-negotiation. If auto-negotiation is successful
* then the link-up status bit will be set and the flow control enable
e1e_flush();
msleep(1);
- /* For these adapters, the SW defineable pin 1 is set when the optics
+ /*
+ * For these adapters, the SW definable pin 1 is set when the optics
* detect a signal. If we have a signal, then poll for a "Link-Up"
* indication.
*/
*
* Sets the flow control high/low threshold (watermark) registers. If
* flow control XON frame transmission is enabled, then set XON frame
- * tansmission as well.
+ * transmission as well.
**/
s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
{
struct e1000_mac_info *mac = &hw->mac;
u32 fcrtl = 0, fcrth = 0;
- /* Set the flow control receive threshold registers. Normally,
+ /*
+ * Set the flow control receive threshold registers. Normally,
* these registers will be set to a default threshold that may be
* adjusted later by the driver's runtime code. However, if the
* ability to transmit pause frames is not enabled, then these
* registers will be set to 0.
*/
if (mac->fc & e1000_fc_tx_pause) {
- /* We need to set up the Receive Threshold high and low water
+ /*
+ * We need to set up the Receive Threshold high and low water
* marks as well as (optionally) enabling the transmission of
* XON frames.
*/
ctrl = er32(CTRL);
- /* Because we didn't get link via the internal auto-negotiation
+ /*
+ * Because we didn't get link via the internal auto-negotiation
* mechanism (we either forced link or we got link via PHY
* auto-neg), we have to manually enable/disable transmit an
* receive flow control.
* frames but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* frames but we do not receive pause frames).
- * 3: Both Rx and TX flow control (symmetric) is enabled.
+ * 3: Both Rx and Tx flow control (symmetric) is enabled.
* other: No other values should be possible at this point.
*/
hw_dbg(hw, "mac->fc = %u\n", mac->fc);
u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
u16 speed, duplex;
- /* Check for the case where we have fiber media and auto-neg failed
+ /*
+ * Check for the case where we have fiber media and auto-neg failed
* so we had to force link. In this case, we need to force the
* configuration of the MAC to match the "fc" parameter.
*/
return ret_val;
}
- /* Check for the case where we have copper media and auto-neg is
+ /*
+ * Check for the case where we have copper media and auto-neg is
* enabled. In this case, we need to check and see if Auto-Neg
* has completed, and if so, how the PHY and link partner has
* flow control configured.
*/
if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) {
- /* Read the MII Status Register and check to see if AutoNeg
+ /*
+ * Read the MII Status Register and check to see if AutoNeg
* has completed. We read this twice because this reg has
* some "sticky" (latched) bits.
*/
return ret_val;
}
- /* The AutoNeg process has completed, so we now need to
+ /*
+ * The AutoNeg process has completed, so we now need to
* read both the Auto Negotiation Advertisement
* Register (Address 4) and the Auto_Negotiation Base
* Page Ability Register (Address 5) to determine how
if (ret_val)
return ret_val;
- /* Two bits in the Auto Negotiation Advertisement Register
+ /*
+ * Two bits in the Auto Negotiation Advertisement Register
* (Address 4) and two bits in the Auto Negotiation Base
* Page Ability Register (Address 5) determine flow control
* for both the PHY and the link partner. The following
* 1 | 1 | 0 | 0 | e1000_fc_none
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
*
- */
- /* Are both PAUSE bits set to 1? If so, this implies
+ *
+ * Are both PAUSE bits set to 1? If so, this implies
* Symmetric Flow Control is enabled at both ends. The
* ASM_DIR bits are irrelevant per the spec.
*
*/
if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
- /* Now we need to check if the user selected RX ONLY
+ /*
+ * Now we need to check if the user selected Rx ONLY
* of pause frames. In this case, we had to advertise
- * FULL flow control because we could not advertise RX
+ * FULL flow control because we could not advertise Rx
* ONLY. Hence, we must now check to see if we need to
* turn OFF the TRANSMISSION of PAUSE frames.
*/
"RX PAUSE frames only.\r\n");
}
}
- /* For receiving PAUSE frames ONLY.
+ /*
+ * For receiving PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
mac->fc = e1000_fc_tx_pause;
hw_dbg(hw, "Flow Control = TX PAUSE frames only.\r\n");
}
- /* For transmitting PAUSE frames ONLY.
+ /*
+ * For transmitting PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
hw_dbg(hw, "Flow Control = NONE.\r\n");
}
- /* Now we need to do one last check... If we auto-
+ /*
+ * Now we need to do one last check... If we auto-
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
if (duplex == HALF_DUPLEX)
mac->fc = e1000_fc_none;
- /* Now we call a subroutine to actually force the MAC
+ /*
+ * Now we call a subroutine to actually force the MAC
* controller to use the correct flow control settings.
*/
ret_val = e1000e_force_mac_fc(hw);
ledctl_blink = E1000_LEDCTL_LED0_BLINK |
(E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
} else {
- /* set the blink bit for each LED that's "on" (0x0E)
- * in ledctl_mode2 */
+ /*
+ * set the blink bit for each LED that's "on" (0x0E)
+ * in ledctl_mode2
+ */
ledctl_blink = hw->mac.ledctl_mode2;
for (i = 0; i < 4; i++)
if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
else
mac->current_ifs_val +=
mac->ifs_step_size;
- ew32(AIT,
- mac->current_ifs_val);
+ ew32(AIT, mac->current_ifs_val);
}
}
} else {
udelay(1);
timeout = NVM_MAX_RETRY_SPI;
- /* Read "Status Register" repeatedly until the LSB is cleared.
+ /*
+ * Read "Status Register" repeatedly until the LSB is cleared.
* The EEPROM will signal that the command has been completed
* by clearing bit 0 of the internal status register. If it's
- * not cleared within 'timeout', then error out. */
+ * not cleared within 'timeout', then error out.
+ */
while (timeout) {
e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
hw->nvm.opcode_bits);
u32 i, eerd = 0;
s32 ret_val = 0;
- /* A check for invalid values: offset too large, too many words,
- * and not enough words. */
+ /*
+ * A check for invalid values: offset too large, too many words,
+ * too many words for the offset, and not enough words.
+ */
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
hw_dbg(hw, "nvm parameter(s) out of bounds\n");
if (ret_val)
break;
- data[i] = (er32(EERD) >>
- E1000_NVM_RW_REG_DATA);
+ data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
}
return ret_val;
s32 ret_val;
u16 widx = 0;
- /* A check for invalid values: offset too large, too many words,
- * and not enough words. */
+ /*
+ * A check for invalid values: offset too large, too many words,
+ * and not enough words.
+ */
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
hw_dbg(hw, "nvm parameter(s) out of bounds\n");
e1000_standby_nvm(hw);
- /* Some SPI eeproms use the 8th address bit embedded in the
- * opcode */
+ /*
+ * Some SPI eeproms use the 8th address bit embedded in the
+ * opcode
+ */
if ((nvm->address_bits == 8) && (offset >= 128))
write_opcode |= NVM_A8_OPCODE_SPI;
/* Check for an alternate MAC address. An alternate MAC
* address can be setup by pre-boot software and must be
* treated like a permanent address and must override the
- * actual permanent MAC address. */
+ * actual permanent MAC address.*/
ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
- &mac_addr_offset);
+ &mac_addr_offset);
if (ret_val) {
hw_dbg(hw, "NVM Read Error\n");
return ret_val;
mac_addr_offset += ETH_ALEN/sizeof(u16);
/* make sure we have a valid mac address here
- * before using it */
+ * before using it */
ret_val = e1000_read_nvm(hw, mac_addr_offset, 1,
&nvm_data);
if (ret_val) {
}
if (mac_addr_offset)
- hw->dev_spec.e82571.alt_mac_addr_is_present = 1;
+ hw->dev_spec.e82571.alt_mac_addr_is_present = 1;
}
for (i = 0; i < ETH_ALEN; i += 2) {
}
/**
- * e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX
+ * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
* @hw: pointer to the HW structure
*
* Enables packet filtering on transmit packets if manageability is enabled
return 0;
}
- /* If we can't read from the host interface for whatever
+ /*
+ * If we can't read from the host interface for whatever
* reason, disable filtering.
*/
ret_val = e1000_mng_enable_host_if(hw);
hdr->checksum = 0;
csum = e1000_calculate_checksum((u8 *)hdr,
E1000_MNG_DHCP_COOKIE_LENGTH);
- /* If either the checksums or signature don't match, then
+ /*
+ * If either the checksums or signature don't match, then
* the cookie area isn't considered valid, in which case we
* take the safe route of assuming Tx filtering is enabled.
*/
/* Calculate length in DWORDs */
length >>= 2;
- /* The device driver writes the relevant command block into the
- * ram area. */
+ /*
+ * The device driver writes the relevant command block into the
+ * ram area.
+ */
for (i = 0; i < length; i++) {
for (j = 0; j < sizeof(u32); j++) {
*(tmp + j) = *bufptr++;
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