cxl: Fix timebase synchronization status on P9

[linux-2.6-block.git] / drivers / misc / cxl / pci.c

diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index e7ac78e854940a3e03d781c81174caf5fe981f05..83f1d08058fc234dc9b141b543084ece35c53b0f 100644 (file)
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -659,9 +659,6 @@ static u64 timebase_read_xsl(struct cxl *adapter)
 
 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
 {
-       u64 psl_tb;
-       int delta;
-       unsigned int retry = 0;
        struct device_node *np;
 
        adapter->psl_timebase_synced = false;
@@ -689,20 +686,6 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
        cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
        cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
 
-       /* Wait until CORE TB and PSL TB difference <= 16usecs */
-       do {
-               msleep(1);
-               if (retry++ > 5) {
-                       dev_info(&dev->dev, "PSL timebase can't synchronize\n");
-                       return;
-               }
-               psl_tb = adapter->native->sl_ops->timebase_read(adapter);
-               delta = mftb() - psl_tb;
-               if (delta < 0)
-                       delta = -delta;
-       } while (tb_to_ns(delta) > 16000);
-
-       adapter->psl_timebase_synced = true;
        return;
 }