arm64: add ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap

[linux-2.6-block.git] / drivers / irqchip / irq-gic-v3.c

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 997104d4338e7fd43673a019b50f71a206f867fb..3779836737c89aa0c70fe88347bf66eafc265970 100644 (file)
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -89,15 +89,6 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
  */
 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
 
-/*
- * Global static key controlling whether an update to PMR allowing more
- * interrupts requires to be propagated to the redistributor (DSB SY).
- * And this needs to be exported for modules to be able to enable
- * interrupts...
- */
-DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
-EXPORT_SYMBOL(gic_pmr_sync);
-
 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
 EXPORT_SYMBOL(gic_nonsecure_priorities);
 
@@ -1768,16 +1759,8 @@ static void gic_enable_nmi_support(void)
        for (i = 0; i < gic_data.ppi_nr; i++)
                refcount_set(&ppi_nmi_refs[i], 0);
 
-       /*
-        * Linux itself doesn't use 1:N distribution, so has no need to
-        * set PMHE. The only reason to have it set is if EL3 requires it
-        * (and we can't change it).
-        */
-       if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
-               static_branch_enable(&gic_pmr_sync);
-
        pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
-               static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
+               gic_has_relaxed_pmr_sync() ? "relaxed" : "forced");
 
        /*
         * How priority values are used by the GIC depends on two things: