Merge tag 'drm-msm-fixes-2023-05-17' of https://gitlab.freedesktop.org/drm/msm into...

[linux-block.git] / drivers / iommu / arm / arm-smmu / arm-smmu-qcom.c

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index d1b296b95c8600df0b658600914c22041229955c..c71afda79d6442f57026b945fd7ff8fe08cd35a4 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -268,12 +268,26 @@ static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 
 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
 {
-       unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
        struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+       unsigned int last_s2cr;
        u32 reg;
        u32 smr;
        int i;
 
+       /*
+        * Some platforms support more than the Arm SMMU architected maximum of
+        * 128 stream matching groups. For unknown reasons, the additional
+        * groups don't exhibit the same behavior as the architected registers,
+        * so limit the groups to 128 until the behavior is fixed for the other
+        * groups.
+        */
+       if (smmu->num_mapping_groups > 128) {
+               dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
+               smmu->num_mapping_groups = 128;
+       }
+
+       last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
+
        /*
         * With some firmware versions writes to S2CR of type FAULT are
         * ignored, and writing BYPASS will end up written as FAULT in the
@@ -503,6 +517,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
        { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
        { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
        { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
+       { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
        { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
        { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
        { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
@@ -547,5 +562,14 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
        if (match)
                return qcom_smmu_create(smmu, match->data);
 
+       /*
+        * If you hit this WARN_ON() you are missing an entry in the
+        * qcom_smmu_impl_of_match[] table, and GPU per-process page-
+        * tables will be broken.
+        */
+       WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),
+            "Missing qcom_smmu_impl_of_match entry for: %s",
+            dev_name(smmu->dev));
+
        return smmu;
 }