drm/radeon: use pcie functions for link width

[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 1907c950d76f05ef32811685baaee9f7d4db83b9..85c604d2923584370e59c88630bed491c2453b48 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7082,9 +7082,10 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 static void si_pcie_gen3_enable(struct radeon_device *rdev)
 {
        struct pci_dev *root = rdev->pdev->bus->self;
+       enum pci_bus_speed speed_cap;
        int bridge_pos, gpu_pos;
-       u32 speed_cntl, mask, current_data_rate;
-       int ret, i;
+       u32 speed_cntl, current_data_rate;
+       int i;
        u16 tmp16;
 
        if (pci_is_root_bus(rdev->pdev->bus))
@@ -7099,23 +7100,24 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
        if (!(rdev->flags & RADEON_IS_PCIE))
                return;
 
-       ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-       if (ret != 0)
+       speed_cap = pcie_get_speed_cap(root);
+       if (speed_cap == PCI_SPEED_UNKNOWN)
                return;
 
-       if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+       if ((speed_cap != PCIE_SPEED_8_0GT) &&
+           (speed_cap != PCIE_SPEED_5_0GT))
                return;
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
        current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
                LC_CURRENT_DATA_RATE_SHIFT;
-       if (mask & DRM_PCIE_SPEED_80) {
+       if (speed_cap == PCIE_SPEED_8_0GT) {
                if (current_data_rate == 2) {
                        DRM_INFO("PCIE gen 3 link speeds already enabled\n");
                        return;
                }
                DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
-       } else if (mask & DRM_PCIE_SPEED_50) {
+       } else if (speed_cap == PCIE_SPEED_5_0GT) {
                if (current_data_rate == 1) {
                        DRM_INFO("PCIE gen 2 link speeds already enabled\n");
                        return;
@@ -7131,7 +7133,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
        if (!gpu_pos)
                return;
 
-       if (mask & DRM_PCIE_SPEED_80) {
+       if (speed_cap == PCIE_SPEED_8_0GT) {
                /* re-try equalization if gen3 is not already enabled */
                if (current_data_rate != 2) {
                        u16 bridge_cfg, gpu_cfg;
@@ -7219,9 +7221,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
 
        pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
        tmp16 &= ~0xf;
-       if (mask & DRM_PCIE_SPEED_80)
+       if (speed_cap == PCIE_SPEED_8_0GT)
                tmp16 |= 3; /* gen3 */
-       else if (mask & DRM_PCIE_SPEED_50)
+       else if (speed_cap == PCIE_SPEED_5_0GT)
                tmp16 |= 2; /* gen2 */
        else
                tmp16 |= 1; /* gen1 */