drm/radeon: Prefer pcie_capability_read_word()

[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 529e70a42019361859a29f96c76238641a10888a..67a98b3370d1ad60973985e14ca94ed93a9770d6 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3257,7 +3257,7 @@ static void si_gpu_init(struct radeon_device *rdev)
                /* XXX what about 12? */
                rdev->config.si.tile_config |= (3 << 0);
                break;
-       }       
+       }
        switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
        case 0: /* four banks */
                rdev->config.si.tile_config |= 0 << 4;
@@ -7087,7 +7087,6 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
 {
        struct pci_dev *root = rdev->pdev->bus->self;
        enum pci_bus_speed speed_cap;
-       int bridge_pos, gpu_pos;
        u32 speed_cntl, current_data_rate;
        int i;
        u16 tmp16;
@@ -7129,12 +7128,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
                DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
        }
 
-       bridge_pos = pci_pcie_cap(root);
-       if (!bridge_pos)
-               return;
-
-       gpu_pos = pci_pcie_cap(rdev->pdev);
-       if (!gpu_pos)
+       if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
                return;
 
        if (speed_cap == PCIE_SPEED_8_0GT) {
@@ -7144,14 +7138,17 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
                        u16 bridge_cfg2, gpu_cfg2;
                        u32 max_lw, current_lw, tmp;
 
-                       pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
-                       pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
+                       pcie_capability_read_word(root, PCI_EXP_LNKCTL,
+                                                 &bridge_cfg);
+                       pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
+                                                 &gpu_cfg);
 
                        tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
-                       pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
+                       pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
 
                        tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
-                       pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
+                       pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
+                                                  tmp16);
 
                        tmp = RREG32_PCIE(PCIE_LC_STATUS1);
                        max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -7169,15 +7166,23 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
 
                        for (i = 0; i < 10; i++) {
                                /* check status */
-                               pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
+                               pcie_capability_read_word(rdev->pdev,
+                                                         PCI_EXP_DEVSTA,
+                                                         &tmp16);
                                if (tmp16 & PCI_EXP_DEVSTA_TRPND)
                                        break;
 
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
-                               pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL,
+                                                         &bridge_cfg);
+                               pcie_capability_read_word(rdev->pdev,
+                                                         PCI_EXP_LNKCTL,
+                                                         &gpu_cfg);
 
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
-                               pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
+                                                         &bridge_cfg2);
+                               pcie_capability_read_word(rdev->pdev,
+                                                         PCI_EXP_LNKCTL2,
+                                                         &gpu_cfg2);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
                                tmp |= LC_SET_QUIESCE;
@@ -7190,32 +7195,46 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
                                msleep(100);
 
                                /* linkctl */
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL,
+                                                         &tmp16);
                                tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
                                tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
-                               pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
+                               pcie_capability_write_word(root,
+                                                          PCI_EXP_LNKCTL,
+                                                          tmp16);
 
-                               pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
+                               pcie_capability_read_word(rdev->pdev,
+                                                         PCI_EXP_LNKCTL,
+                                                         &tmp16);
                                tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
                                tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
-                               pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
+                               pcie_capability_write_word(rdev->pdev,
+                                                          PCI_EXP_LNKCTL,
+                                                          tmp16);
 
                                /* linkctl2 */
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
+                                                         &tmp16);
                                tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
                                           PCI_EXP_LNKCTL2_TX_MARGIN);
                                tmp16 |= (bridge_cfg2 &
                                          (PCI_EXP_LNKCTL2_ENTER_COMP |
                                           PCI_EXP_LNKCTL2_TX_MARGIN));
-                               pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
+                               pcie_capability_write_word(root,
+                                                          PCI_EXP_LNKCTL2,
+                                                          tmp16);
 
-                               pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
+                               pcie_capability_read_word(rdev->pdev,
+                                                         PCI_EXP_LNKCTL2,
+                                                         &tmp16);
                                tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
                                           PCI_EXP_LNKCTL2_TX_MARGIN);
                                tmp16 |= (gpu_cfg2 &
                                          (PCI_EXP_LNKCTL2_ENTER_COMP |
                                           PCI_EXP_LNKCTL2_TX_MARGIN));
-                               pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
+                               pcie_capability_write_word(rdev->pdev,
+                                                          PCI_EXP_LNKCTL2,
+                                                          tmp16);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
                                tmp &= ~LC_SET_QUIESCE;
@@ -7229,7 +7248,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
        speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
-       pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
+       pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
        tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
        if (speed_cap == PCIE_SPEED_8_0GT)
                tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
@@ -7237,7 +7256,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
                tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
                tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
-       pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
+       pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
        speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;