drm/radeon: clean up vram/gtt location handling

[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_device.c

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 44b8034a400d297dcba86012c8dd797f72a6af28..62d0ba338582973c47ac6c6d93bcf6c443e66c0c 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -359,7 +359,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
        uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 
        mc->vram_start = base;
-       if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
+       if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
                dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
                mc->real_vram_size = mc->aper_size;
                mc->mc_vram_size = mc->aper_size;
@@ -394,7 +394,7 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 {
        u64 size_af, size_bf;
 
-       size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
+       size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
        size_bf = mc->vram_start & ~mc->gtt_base_align;
        if (size_bf > size_af) {
                if (mc->gtt_size > size_bf) {
@@ -1068,6 +1068,17 @@ int radeon_device_init(struct radeon_device *rdev,
                radeon_agp_disable(rdev);
        }
 
+       /* Set the internal MC address mask
+        * This is the max address of the GPU's
+        * internal address space.
+        */
+       if (rdev->family >= CHIP_CAYMAN)
+               rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
+       else if (rdev->family >= CHIP_CEDAR)
+               rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
+       else
+               rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
+
        /* set DMA mask + need_dma32 flags.
         * PCIE - can handle 40-bits.
         * IGP - can handle 40-bits